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[Qemu-commits] [qemu/qemu] 9cf3bc: hw/i2c: Implement Broadcom Serial Con
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 9cf3bc: hw/i2c: Implement Broadcom Serial Controller (BSC) |
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Date: |
Tue, 05 Mar 2024 07:26:13 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 9cf3bc65afdb63f6fc28560274600b4e6e0c91ca
https://github.com/qemu/qemu/commit/9cf3bc65afdb63f6fc28560274600b4e6e0c91ca
Author: Rayhan Faizel <rayhan.faizel@gmail.com>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M docs/system/arm/raspi.rst
M hw/i2c/Kconfig
A hw/i2c/bcm2835_i2c.c
M hw/i2c/meson.build
A include/hw/i2c/bcm2835_i2c.h
Log Message:
-----------
hw/i2c: Implement Broadcom Serial Controller (BSC)
A few deficiencies in the current device model need to be noted.
1. FIFOs are not used. All sends and receives are done directly.
2. Repeated starts are not emulated. Repeated starts can be triggered in real
hardware by sending a new read transfer request in the window time between
transfer active set of write transfer request and done bit set of the same.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240224191038.2409945-2-rayhan.faizel@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f5c6320bf7b4b064e3368268e9e475f8415559f6
https://github.com/qemu/qemu/commit/f5c6320bf7b4b064e3368268e9e475f8415559f6
Author: Rayhan Faizel <rayhan.faizel@gmail.com>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M hw/arm/Kconfig
M hw/arm/bcm2835_peripherals.c
M include/hw/arm/bcm2835_peripherals.h
Log Message:
-----------
hw/arm: Connect BSC to BCM2835 board as I2C0, I2C1 and I2C2
BCM2835 has three I2C controllers. All of them share the same interrupt line.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240224191038.2409945-3-rayhan.faizel@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0820e097fa844b13e9246c1210b89265a0e0cc5b
https://github.com/qemu/qemu/commit/0820e097fa844b13e9246c1210b89265a0e0cc5b
Author: Rayhan Faizel <rayhan.faizel@gmail.com>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
A tests/qtest/bcm2835-i2c-test.c
M tests/qtest/meson.build
Log Message:
-----------
tests/qtest: Add testcase for BCM2835 BSC
Simple testcase for validating proper operation of read and write for all
three BSC controllers.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240224191038.2409945-4-rayhan.faizel@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f576e0733ccb023cde94acc7897c78a4871a09d0
https://github.com/qemu/qemu/commit/f576e0733ccb023cde94acc7897c78a4871a09d0
Author: Tong Ho <tong.ho@amd.com>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M hw/char/pl011.c
Log Message:
-----------
hw/char/pl011: Add support for loopback
This patch adds loopback for sent characters, sent BREAK,
and modem-control signals.
Loopback of send and modem-control is often used for uart
self tests in real hardware but missing from current pl011
model, resulting in self-test failures when running in QEMU.
This implementation matches what is observed in real pl011
hardware placed in loopback mode:
1. Input characters and BREAK events from serial backend
are ignored, but
2. Both TX characters and BREAK events are still sent to
serial backend, in addition to be looped back to RX.
Signed-off-by: Tong Ho <tong.ho@amd.com>
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20240227054855.44204-1-tong.ho@amd.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d6b55a0fe9920b46d380f50d7da48ff43de21324
https://github.com/qemu/qemu/commit/d6b55a0fe9920b46d380f50d7da48ff43de21324
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M MAINTAINERS
M docs/system/arm/b-l475e-iot01a.rst
M hw/arm/Kconfig
M hw/arm/stm32l4x5_soc.c
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/stm32l4x5_rcc.c
M hw/misc/trace-events
M include/hw/arm/stm32l4x5_soc.h
A include/hw/misc/stm32l4x5_rcc.h
A include/hw/misc/stm32l4x5_rcc_internals.h
Log Message:
-----------
hw/misc/stm32l4x5_rcc: Implement STM32L4x5_RCC skeleton
Add the necessary files to add a simple RCC implementation with just
reads from and writes to registers. Also instantiate the RCC in the
STM32L4x5_SoC. It is needed for accurate emulation of all the SoC
clocks and timers.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240303140643.81957-2-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ec7d83acbd1182d47df742745b43e6b16a3a4977
https://github.com/qemu/qemu/commit/ec7d83acbd1182d47df742745b43e6b16a3a4977
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M hw/misc/stm32l4x5_rcc.c
M hw/misc/trace-events
M include/hw/misc/stm32l4x5_rcc.h
M include/hw/misc/stm32l4x5_rcc_internals.h
Log Message:
-----------
hw/misc/stm32l4x5_rcc: Add an internal clock multiplexer object
This object is used to represent every multiplexer in the clock tree as
well as every clock output, every presecaler, frequency multiplier, etc.
This allows to use a generic approach for every component of the clock tree
(except the PLLs).
The migration handling is based on hw/misc/zynq_sclr.c.
Three phase reset will be handled in a later commit.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20240303140643.81957-3-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6487653efd54ea16c9fa39f0f7a648f27bc2c548
https://github.com/qemu/qemu/commit/6487653efd54ea16c9fa39f0f7a648f27bc2c548
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M hw/misc/stm32l4x5_rcc.c
M hw/misc/trace-events
M include/hw/misc/stm32l4x5_rcc.h
M include/hw/misc/stm32l4x5_rcc_internals.h
Log Message:
-----------
hw/misc/stm32l4x5_rcc: Add an internal PLL Clock object
This object represents the PLLs and their channels. The PLLs allow for a
more fine-grained control of the clocks frequency.
The migration handling is based on hw/misc/zynq_sclr.c.
Three phase reset will be handled in a later commit.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240303140643.81957-4-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 141c29a23bb8eb63c04199a2c3653195ca14f76a
https://github.com/qemu/qemu/commit/141c29a23bb8eb63c04199a2c3653195ca14f76a
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M hw/misc/stm32l4x5_rcc.c
M include/hw/misc/stm32l4x5_rcc_internals.h
Log Message:
-----------
hw/misc/stm32l4x5_rcc: Initialize PLLs and clock multiplexers
Instantiate the whole clock tree and using the Clock multiplexers and
the PLLs defined in the previous commits. This allows to statically
define the clock tree and easily follow the clock signal from one end to
another.
Also handle three-phase reset now that we have defined a known base
state for every object.
(Reset handling based on hw/misc/zynq_sclr.c)
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240303140643.81957-5-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9c796d503f9d2ee2f6948964d972a7ef23b62033
https://github.com/qemu/qemu/commit/9c796d503f9d2ee2f6948964d972a7ef23b62033
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M hw/misc/stm32l4x5_rcc.c
Log Message:
-----------
hw/misc/stm32l4x5_rcc: Handle Register Updates
Update the RCC state and propagate frequency changes when writing to the
RCC registers. Currently, ICSCR, CIER, the reset registers and the stop
mode registers are not implemented.
Some fields have not been implemented due to uncertainty about
how to handle them (Like the clock security system or bypassing
mecanisms).
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240303140643.81957-6-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3b551477172801bbfb78bf8f58c512307785fd9e
https://github.com/qemu/qemu/commit/3b551477172801bbfb78bf8f58c512307785fd9e
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M hw/misc/stm32l4x5_rcc.c
Log Message:
-----------
hw/misc/stm32l4x5_rcc: Add write protections to CR register
Add write protections for the fields in the CR register.
PLL configuration write protections (among others) have not
been handled yet. This is planned in a future patch set.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240303140643.81957-7-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 60849fe4a79df0834c86aaa6669e1b64feb6150e
https://github.com/qemu/qemu/commit/60849fe4a79df0834c86aaa6669e1b64feb6150e
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M hw/arm/b-l475e-iot01a.c
M hw/arm/stm32l4x5_soc.c
M include/hw/arm/stm32l4x5_soc.h
Log Message:
-----------
hw/arm/stm32l4x5_soc.c: Use the RCC Sysclk
Now that we can generate reliable clock frequencies from the RCC, remove
the hacky definition of the sysclk in the b_l475e_iot01a initialisation
code and use the correct RCC clock.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240303140643.81957-8-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 13d6c073f067d3465010eb54cc908c05ffbc84f1
https://github.com/qemu/qemu/commit/13d6c073f067d3465010eb54cc908c05ffbc84f1
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/stm32l4x5_rcc-test.c
Log Message:
-----------
tests/qtest/stm32l4x5_rcc-test.c: Add tests for the STM32L4x5_RCC
Tests:
- the ability to change the sysclk of the device
- the ability to enable/disable/configure the PLLs
- if the clock multiplexers work
- the register flags and the generation of irqs
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-id: 20240303140643.81957-9-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 707ded20a23e877a32c4acf47ea68819be0637a5
https://github.com/qemu/qemu/commit/707ded20a23e877a32c4acf47ea68819be0637a5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Support 32-byte alignment in pow2_align
Now that we have removed TARGET_PAGE_BITS_MIN-6 from
TLB_FLAGS_MASK, we can test for 32-byte alignment.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301204110.656742-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a1a85a9502b5d0011320fdf490c1d6bc2f8fdc79
https://github.com/qemu/qemu/commit/a1a85a9502b5d0011320fdf490c1d6bc2f8fdc79
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M include/exec/memattrs.h
Log Message:
-----------
exec/memattrs: Remove target_tlb_bit*
These fields are no longer used since 937f224559.
Target specific extensions to the page tables should be done
with TARGET_PAGE_ENTRY_EXTRA.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301204110.656742-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a0ff4a879cd3198adb4213653d51a39d053ef2d6
https://github.com/qemu/qemu/commit/a0ff4a879cd3198adb4213653d51a39d053ef2d6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/memattrs.h
M include/hw/core/cpu.h
M target/sparc/mmu_helper.c
Log Message:
-----------
accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull
Allow the target to set tlb flags to apply to all of the
comparators. Remove MemTxAttrs.byte_swap, as the bit is
not relevant to memory transactions, only the page mapping.
Adjust target/sparc to set TLB_BSWAP directly.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301204110.656742-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 49fa457ca5abc8c46910ec777e2c510b428a1648
https://github.com/qemu/qemu/commit/49fa457ca5abc8c46910ec777e2c510b428a1648
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/cpu-all.h
Log Message:
-----------
accel/tcg: Add TLB_CHECK_ALIGNED
This creates a per-page method for checking of alignment.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301204110.656742-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 59754f85ed35cbd5f4bf2663ca2136c78d5b2413
https://github.com/qemu/qemu/commit/59754f85ed35cbd5f4bf2663ca2136c78d5b2413
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M target/arm/tcg/hflags.c
Log Message:
-----------
target/arm: Do memory type alignment check when translation disabled
If translation is disabled, the default memory type is Device, which
requires alignment checking. This is more optimally done early via
the MemOp given to the TCG memory operation.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reported-by: Idan Horowitz <idan.horowitz@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301204110.656742-6-richard.henderson@linaro.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1204
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 728b923f548dba640cecb693ff1f1f134ef1097a
https://github.com/qemu/qemu/commit/728b923f548dba640cecb693ff1f1f134ef1097a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Do memory type alignment check when translation enabled
If translation is enabled, and the PTE memory type is Device,
enable checking alignment via TLB_CHECK_ALIGNMENT. While the
check is done later than it should be per the ARM, it's better
than not performing the check at all.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301204110.656742-7-richard.henderson@linaro.org
[PMM: tweaks to comment text]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d346feed696c536f178f8110666e2bcc4c21b983
https://github.com/qemu/qemu/commit/d346feed696c536f178f8110666e2bcc4c21b983
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M include/qemu/atomic.h
Log Message:
-----------
atomic.h: Reword confusing comment for qatomic_cmpxchg
The qatomic_cmpxchg() and qatomic_cmpxchg__nocheck() macros have
a comment that reads:
Returns the eventual value, failed or not
This is somewhere between cryptic and wrong, since the value actually
returned is the value that was in memory before the cmpxchg. Reword
to match how we describe these macros in atomics.rst.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-id: 20240223182035.1048541-1-peter.maydell@linaro.org
Commit: 7558300c53057126514ee0fd5cf629c65ccc20e1
https://github.com/qemu/qemu/commit/7558300c53057126514ee0fd5cf629c65ccc20e1
Author: Steven Shen <steven.shen@jaguarmicro.com>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M qemu-options.hx
Log Message:
-----------
qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports
Before v2.12, the implementation of serial ports was limited to
a value of MAX_SERIAL_PORTS = 4. We now dynamically allocate
the data structures for serial ports, so this limit is no longer
present, but the documentation for the -serial options still reads:
"This option can be used several times to simulate up to 4 serial ports."
Update to "This option can be used several times to simulate
multiple serial ports." to avoid misleading.
Signed-off-by: Steven Shen <steven.shen@jaguarmicro.com>
Message-id: 20240305013016.2268-1-steven.shen@jaguarmicro.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: db596ae19040574e41d086e78469014191d7d7fc
https://github.com/qemu/qemu/commit/db596ae19040574e41d086e78469014191d7d7fc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-05 (Tue, 05 Mar 2024)
Changed paths:
M MAINTAINERS
M accel/tcg/cputlb.c
M docs/system/arm/b-l475e-iot01a.rst
M docs/system/arm/raspi.rst
M hw/arm/Kconfig
M hw/arm/b-l475e-iot01a.c
M hw/arm/bcm2835_peripherals.c
M hw/arm/stm32l4x5_soc.c
M hw/char/pl011.c
M hw/i2c/Kconfig
A hw/i2c/bcm2835_i2c.c
M hw/i2c/meson.build
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/stm32l4x5_rcc.c
M hw/misc/trace-events
M include/exec/cpu-all.h
M include/exec/memattrs.h
M include/hw/arm/bcm2835_peripherals.h
M include/hw/arm/stm32l4x5_soc.h
M include/hw/core/cpu.h
A include/hw/i2c/bcm2835_i2c.h
A include/hw/misc/stm32l4x5_rcc.h
A include/hw/misc/stm32l4x5_rcc_internals.h
M include/qemu/atomic.h
M qemu-options.hx
M target/arm/ptw.c
M target/arm/tcg/hflags.c
M target/arm/tcg/translate.c
M target/sparc/mmu_helper.c
A tests/qtest/bcm2835-i2c-test.c
M tests/qtest/meson.build
A tests/qtest/stm32l4x5_rcc-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20240305' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* raspi: Implement Broadcom Serial Controller (BSC) for BCM2835 boards
* hw/char/pl011: Add support for loopback
* STM32L4x5: Implement RCC clock control device
* target/arm: Do memory type alignment checks
* atomic.h: Reword confusing comment for qatomic_cmpxchg
* qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 05 Mar 2024 13:52:08 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20240305' of
https://git.linaro.org/people/pmaydell/qemu-arm:
qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports
atomic.h: Reword confusing comment for qatomic_cmpxchg
target/arm: Do memory type alignment check when translation enabled
target/arm: Do memory type alignment check when translation disabled
accel/tcg: Add TLB_CHECK_ALIGNED
accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull
exec/memattrs: Remove target_tlb_bit*
target/arm: Support 32-byte alignment in pow2_align
tests/qtest/stm32l4x5_rcc-test.c: Add tests for the STM32L4x5_RCC
hw/arm/stm32l4x5_soc.c: Use the RCC Sysclk
hw/misc/stm32l4x5_rcc: Add write protections to CR register
hw/misc/stm32l4x5_rcc: Handle Register Updates
hw/misc/stm32l4x5_rcc: Initialize PLLs and clock multiplexers
hw/misc/stm32l4x5_rcc: Add an internal PLL Clock object
hw/misc/stm32l4x5_rcc: Add an internal clock multiplexer object
hw/misc/stm32l4x5_rcc: Implement STM32L4x5_RCC skeleton
hw/char/pl011: Add support for loopback
tests/qtest: Add testcase for BCM2835 BSC
hw/arm: Connect BSC to BCM2835 board as I2C0, I2C1 and I2C2
hw/i2c: Implement Broadcom Serial Controller (BSC)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/7d4e29ef805f...db596ae19040
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