[Qemu-devel] [PATCH v4 08/29] target-ppc: Add HID4 SPR for PPC970

[Alexey Kardashevskiy]

Previously LPCR was registered for the 970 class which was wrong as
it does not have LPCR. Instead, HID4 is used which this patch registers.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
 target-ppc/cpu.h            |  1 +
 target-ppc/translate_init.c | 11 +++++++++++
 2 files changed, 12 insertions(+)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index fc09087..97f01ca 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1683,6 +1683,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
 #define SPR_750_TDCL          (0x3F4)
 #define SPR_40x_IAC1          (0x3F4)
 #define SPR_MMUCSR0           (0x3F4)
+#define SPR_970_HID4          (0x3F4)
 #define SPR_DABR              (0x3F5)
 #define DABR_MASK (~(target_ulong)0x7)
 #define SPR_Exxx_BUCSR        (0x3F5)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 0fcf918..de920a0 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7301,6 +7301,16 @@ static void gen_spr_970_hior(CPUPPCState *env)
                  0x00000000);
 }
 
+static void gen_spr_970_lpar(CPUPPCState *env)
+{
+    /* Logical partitionning */
+    /* PPC970: HID4 is effectively the LPCR */
+    spr_register(env, SPR_970_HID4, "HID4",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+}
+
 static void gen_spr_book3s_common(CPUPPCState *env)
 {
     spr_register(env, SPR_CTRL, "SPR_CTRL",
@@ -7490,6 +7500,7 @@ static void init_proc_970 (CPUPPCState *env)
     gen_spr_book3s_common(env);
     gen_spr_970_pmu_hypv(env);
     gen_spr_970_pmu_user(env);
+    gen_spr_970_lpar(env);
 
     gen_spr_power5p_ear(env);
 
-- 
2.0.0