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Re: [Qemu-devel] [PATCH v4 27/29] target-ppc: Enable DABRX SPR and limit
From: |
Alexey Kardashevskiy |
Subject: |
Re: [Qemu-devel] [PATCH v4 27/29] target-ppc: Enable DABRX SPR and limit it to <=POWER7 |
Date: |
Wed, 04 Jun 2014 13:12:14 +1000 |
User-agent: |
Mozilla/5.0 (X11; Linux i686 on x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 06/04/2014 04:05 AM, Tom Musta wrote:
> On 6/3/2014 4:28 AM, Alexey Kardashevskiy wrote:
>> This adds DABRX SPR.
>>
>> As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not
>> have them (as it implements more powerful facility instead), this limits
>> DABR/DABRX registration by POWER7 (inclusive).
>>
>> Signed-off-by: Alexey Kardashevskiy <address@hidden>
>> ---
>> target-ppc/translate_init.c | 9 ++++++++-
>> 1 file changed, 8 insertions(+), 1 deletion(-)
>>
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 237074d..2c076b0 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7415,6 +7415,11 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
>> SPR_NOACCESS, SPR_NOACCESS,
>> &spr_read_generic, &spr_write_generic,
>> KVM_REG_PPC_DABR, 0x00000000);
>> +
>> + spr_register_kvm(env, SPR_DABRX, "DABRX",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + KVM_REG_PPC_DABRX, 0x00000000);
>> }
>>
>
> Is no read nor write access in any mode what you intended? It appears
> to be supervisor read/write in the 970 UM.
This is worse actually:
970 says it is super/write and super/read
powerisa 2.03..2.04 say it is hypv/write and super/read.
powerisa 2.05 and newer say it is hypv/write and hypv/read.
I can make it the same as DABR for now and fix this somehow when I'll be
adding H_SET_XDABR, will this be ok?
>> static void gen_spr_970_dbg(CPUPPCState *env)
>> @@ -7784,7 +7789,6 @@ static void init_proc_book3s_64(CPUPPCState *env, int
>> version)
>> gen_spr_book3s_altivec(env);
>> gen_spr_book3s_pmu_hypv(env);
>> gen_spr_book3s_pmu_user(env);
>> - gen_spr_book3s_dbg(env);
>> gen_spr_book3s_common(env);
>>
>> switch (version) {
>> @@ -7827,6 +7831,9 @@ static void init_proc_book3s_64(CPUPPCState *env, int
>> version)
>> gen_spr_power8_pmu_user(env);
>> gen_spr_power8_tm(env);
>> }
>> + if (version < BOOK3S_CPU_POWER8) {
>> + gen_spr_book3s_dbg(env);
>> + }
>> #if !defined(CONFIG_USER_ONLY)
>> switch (version) {
>> case BOOK3S_CPU_970:
>>
>
--
Alexey
[Qemu-devel] [PATCH v4 29/29] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE, Alexey Kardashevskiy, 2014/06/03
[Qemu-devel] [PATCH v4 25/29] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs, Alexey Kardashevskiy, 2014/06/03
[Qemu-devel] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs, Alexey Kardashevskiy, 2014/06/03