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[Qemu-devel] [PULL 069/118] PPC: Add dcbtls emulation
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 069/118] PPC: Add dcbtls emulation |
Date: |
Wed, 4 Jun 2014 14:44:10 +0200 |
The dcbtls instruction is able to lock data inside the L1 cache.
Unfortunately we don't emulate any caches, so we have to tell the guest
that its locking attempt failed.
However, by implementing the instruction we at least don't give the
guest a program exception which it definitely does not expect.
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6aede79..e205e0c 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4480,6 +4480,17 @@ static void gen_dcbtst(DisasContext *ctx)
*/
}
+/* dcbtls */
+static void gen_dcbtls(DisasContext *ctx)
+{
+ /* Always fails locking the cache */
+ TCGv t0 = tcg_temp_new();
+ gen_load_spr(t0, SPR_Exxx_L1CSR0);
+ tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
+ gen_store_spr(SPR_Exxx_L1CSR0, t0);
+ tcg_temp_free(t0);
+}
+
/* dcbz */
static void gen_dcbz(DisasContext *ctx)
{
@@ -10214,6 +10225,7 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001,
PPC_CACHE),
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
+GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
--
1.8.1.4
- [Qemu-devel] [PULL 065/118] PPC: Add definitions for GIVORs, (continued)
- [Qemu-devel] [PULL 065/118] PPC: Add definitions for GIVORs, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 051/118] target-ppc: Introduce DFP Shift Significand, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 060/118] PPC: e500: some pci related cleanup, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 055/118] util: Add InvMixColumns, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 067/118] PPC: Add L1CFG1 SPR emulation, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 058/118] target-ppc: Refactor AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 064/118] PPC: Make all e500 CPUs SVR aware, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 066/118] PPC: Fix SPR access control of L1CFG0, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 074/118] spapr: Add ibm, chip-id property in device tree, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 069/118] PPC: Add dcbtls emulation,
Alexander Graf <=
- [Qemu-devel] [PULL 073/118] spapr: Add support for time base offset migration, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 061/118] PPC: e500: implement PCI INTx routing, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 072/118] PPC: e500: Move to u-boot as firmware, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 068/118] PPC: Properly emulate L1CSR0 and L1CSR1, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 070/118] PPC: e500: Expose kernel load address in dt, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 071/118] PPC: Add u-boot firmware for e500, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 015/118] libdecnumber: Introduce libdecnumber Code, Alexander Graf, 2014/06/04
- Re: [Qemu-devel] [PULL 00/118] ppc patch queue 2014-06-04, Peter Maydell, 2014/06/05