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[Qemu-devel] [PULL 15/20] target-arm: A32/T32: Mask CRC value in calling
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/20] target-arm: A32/T32: Mask CRC value in calling code, not helper |
Date: |
Mon, 9 Jun 2014 15:57:33 +0100 |
Bring the 32-bit CRC helper functions into line with the A64 ones,
by masking the high bytes of the value in the calling code rather
than the helper. This is more efficient since we can determine the
mask at translation time.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 25 ++++++-------------------
target-arm/translate.c | 10 ++++++++++
2 files changed, 16 insertions(+), 19 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d32d120..2b7a904 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5585,28 +5585,15 @@ int arm_rmode_to_sf(int rmode)
return rmode;
}
-static void crc_init_buffer(uint8_t *buf, uint32_t val, uint32_t bytes)
-{
- memset(buf, 0, 4);
-
- if (bytes == 1) {
- buf[0] = val & 0xff;
- } else if (bytes == 2) {
- buf[0] = val & 0xff;
- buf[1] = (val >> 8) & 0xff;
- } else {
- buf[0] = val & 0xff;
- buf[1] = (val >> 8) & 0xff;
- buf[2] = (val >> 16) & 0xff;
- buf[3] = (val >> 24) & 0xff;
- }
-}
-
+/* CRC helpers.
+ * The upper bytes of val (above the number specified by 'bytes') must have
+ * been zeroed out by the caller.
+ */
uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
{
uint8_t buf[4];
- crc_init_buffer(buf, val, bytes);
+ stl_le_p(buf, val);
/* zlib crc32 converts the accumulator and output to one's complement. */
return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
@@ -5616,7 +5603,7 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,
uint32_t bytes)
{
uint8_t buf[4];
- crc_init_buffer(buf, val, bytes);
+ stl_le_p(buf, val);
/* Linux crc32c converts the output to one's complement. */
return crc32c(acc, buf, bytes) ^ 0xffffffff;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 41c3fc7..351943f 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7806,6 +7806,11 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
tmp = load_reg(s, rn);
tmp2 = load_reg(s, rm);
+ if (op1 == 0) {
+ tcg_gen_andi_i32(tmp2, tmp2, 0xff);
+ } else if (op1 == 1) {
+ tcg_gen_andi_i32(tmp2, tmp2, 0xffff);
+ }
tmp3 = tcg_const_i32(1 << op1);
if (c & 0x2) {
gen_helper_crc32c(tmp, tmp, tmp2, tmp3);
@@ -9438,6 +9443,11 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
}
tmp2 = load_reg(s, rm);
+ if (sz == 0) {
+ tcg_gen_andi_i32(tmp2, tmp2, 0xff);
+ } else if (sz == 1) {
+ tcg_gen_andi_i32(tmp2, tmp2, 0xffff);
+ }
tmp3 = tcg_const_i32(1 << sz);
if (c) {
gen_helper_crc32c(tmp, tmp, tmp2, tmp3);
--
1.9.2
- [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 20/20] target-arm: Delete unused iwmmxt_msadb helper, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 18/20] target-arm: A64: Implement two-register SHA instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 19/20] target-arm: Fix errors in writes to generic timer control registers, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 15/20] target-arm: A32/T32: Mask CRC value in calling code, not helper,
Peter Maydell <=
- [Qemu-devel] [PULL 16/20] target-arm: A64: Implement AES instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 13/20] target-arm: VFPv4 implies half-precision extension, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 14/20] target-arm: A64: Implement CRC instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 11/20] target-arm: Remove unnecessary setting of feature bits, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 09/20] target-arm: A64: Use PMULL feature bit for PMULL, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 10/20] target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 07/20] target-arm: Allow 3reg_wide undefreq to encode more bad size options, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 08/20] target-arm: add support for v8 VMULL.P64 instruction, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 17/20] target-arm: A64: Implement 3-register SHA instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 05/20] target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables, Peter Maydell, 2014/06/09