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[PULL 21/42] target/arm: Convert Neon VSWP to decodetree
From: |
Peter Maydell |
Subject: |
[PULL 21/42] target/arm: Convert Neon VSWP to decodetree |
Date: |
Tue, 23 Jun 2020 12:38:43 +0100 |
Convert the Neon VSWP insn to decodetree. Since the new implementation
doesn't have to share a pass-loop with the other 2-reg-misc operations
we can implement the swap with 64-bit accesses rather than 32-bits
(which brings us into line with the pseudocode and is more efficient).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-20-peter.maydell@linaro.org
---
target/arm/neon-dp.decode | 2 ++
target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++
target/arm/translate.c | 5 +---
3 files changed, 44 insertions(+), 4 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index 5507c3e4623..2f64841de52 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -488,6 +488,8 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 .
op:1 1 .... @1reg_imm
VABS_F 1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc
VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
+ VSWP 1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc
+
VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index 29bc161f36a..01da7fad462 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -3927,3 +3927,44 @@ DO_VCVT(VCVTPU, FPROUNDING_POSINF, false)
DO_VCVT(VCVTPS, FPROUNDING_POSINF, true)
DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false)
DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true)
+
+static bool trans_VSWP(DisasContext *s, arg_2misc *a)
+{
+ TCGv_i64 rm, rd;
+ int pass;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->size != 0) {
+ return false;
+ }
+
+ if ((a->vd | a->vm) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ rm = tcg_temp_new_i64();
+ rd = tcg_temp_new_i64();
+ for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
+ neon_load_reg64(rm, a->vm + pass);
+ neon_load_reg64(rd, a->vd + pass);
+ neon_store_reg64(rm, a->vd + pass);
+ neon_store_reg64(rd, a->vm + pass);
+ }
+ tcg_temp_free_i64(rm);
+ tcg_temp_free_i64(rd);
+
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b0181062020..e8cd4a9c61f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4944,6 +4944,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
case NEON_2RM_VCVTPS:
case NEON_2RM_VCVTMU:
case NEON_2RM_VCVTMS:
+ case NEON_2RM_VSWP:
/* handled by decodetree */
return 1;
case NEON_2RM_VTRN:
@@ -4965,10 +4966,6 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
for (pass = 0; pass < (q ? 4 : 2); pass++) {
tmp = neon_load_reg(rm, pass);
switch (op) {
- case NEON_2RM_VSWP:
- tmp2 = neon_load_reg(rd, pass);
- neon_store_reg(rm, pass, tmp2);
- break;
case NEON_2RM_VTRN:
tmp2 = neon_load_reg(rd, pass);
switch (size) {
--
2.20.1
- [PULL 10/42] target/arm: Convert Neon 2-reg-misc crypto operations to decodetree, (continued)
- [PULL 10/42] target/arm: Convert Neon 2-reg-misc crypto operations to decodetree, Peter Maydell, 2020/06/23
- [PULL 13/42] target/arm: Make gen_swap_half() take separate src and dest, Peter Maydell, 2020/06/23
- [PULL 14/42] target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetree, Peter Maydell, 2020/06/23
- [PULL 12/42] target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefs, Peter Maydell, 2020/06/23
- [PULL 15/42] target/arm: Convert remaining simple 2-reg-misc Neon ops, Peter Maydell, 2020/06/23
- [PULL 16/42] target/arm: Convert Neon VQABS, VQNEG to decodetree, Peter Maydell, 2020/06/23
- [PULL 17/42] target/arm: Convert simple fp Neon 2-reg-misc insns, Peter Maydell, 2020/06/23
- [PULL 18/42] target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetree, Peter Maydell, 2020/06/23
- [PULL 19/42] target/arm: Convert Neon 2-reg-misc VRINT insns to decodetree, Peter Maydell, 2020/06/23
- [PULL 20/42] target/arm: Convert Neon 2-reg-misc VCVT insns to decodetree, Peter Maydell, 2020/06/23
- [PULL 21/42] target/arm: Convert Neon VSWP to decodetree,
Peter Maydell <=
- [PULL 23/42] target/arm: Move some functions used only in translate-neon.inc.c to that file, Peter Maydell, 2020/06/23
- [PULL 24/42] target/arm: Remove unnecessary gen_io_end() calls, Peter Maydell, 2020/06/23
- [PULL 22/42] target/arm: Convert Neon VTRN to decodetree, Peter Maydell, 2020/06/23
- [PULL 25/42] target/arm: Remove dead code relating to SABA and UABA, Peter Maydell, 2020/06/23
- [PULL 26/42] hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status, Peter Maydell, 2020/06/23
- [PULL 28/42] hw/i2c/versatile_i2c: Add SCL/SDA definitions, Peter Maydell, 2020/06/23
- [PULL 27/42] hw/i2c/versatile_i2c: Add definitions for register addresses, Peter Maydell, 2020/06/23
- [PULL 30/42] hw/arm: Use TYPE_VERSATILE_I2C instead of hardcoded string, Peter Maydell, 2020/06/23
- [PULL 29/42] hw/i2c: Add header for ARM SBCon two-wire serial bus interface, Peter Maydell, 2020/06/23
- [PULL 31/42] hw/arm/mps2: Document CMSDK/FPGA APB subsystem sections, Peter Maydell, 2020/06/23