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Re: [PATCH 03/20] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH 03/20] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn |
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Date: |
Mon, 24 Aug 2020 17:40:36 +0100 |
On Sat, 15 Aug 2020 at 02:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Model gen_gvec_fn_zzz on gen_gvec_fn3 in translate-a64.c, but
> indicating which kind of register and in which order.
>
> Model do_zzz_fn on the other do_foo functions that take an
> argument set and verify sve enabled.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- Re: [PATCH 15/20] target/arm: Fix sve_uzp_p vs odd vector lengths, (continued)
- [PATCH 10/20] target/arm: Split out gen_gvec_ool_zzp, Richard Henderson, 2020/08/15
- [PATCH 05/20] target/arm: Merge do_vector2_p into do_mov_p, Richard Henderson, 2020/08/15
- [PATCH 14/20] target/arm: Generalize inl_qrdmlah_* helper functions, Richard Henderson, 2020/08/15
- [PATCH 18/20] target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd, Richard Henderson, 2020/08/15
- [PATCH 03/20] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn, Richard Henderson, 2020/08/15
- Re: [PATCH 03/20] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn,
Peter Maydell <=
- Re: [PATCH 00/20] target/arm: SVE2 preparatory patches, no-reply, 2020/08/15
- Re: [PATCH 00/20] target/arm: SVE2 preparatory patches, Peter Maydell, 2020/08/27