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[PATCH 39/77] target/microblaze: Convert dec_pattern to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH 39/77] target/microblaze: Convert dec_pattern to decodetree |
Date: |
Tue, 25 Aug 2020 13:59:12 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/insns.decode | 4 ++
target/microblaze/translate.c | 67 +++++++++-------------------------
2 files changed, 22 insertions(+), 49 deletions(-)
diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode
index 3f5f7b1852..8d3de039fb 100644
--- a/target/microblaze/insns.decode
+++ b/target/microblaze/insns.decode
@@ -41,6 +41,10 @@ addikc 001110 ..... ..... ................
@typeb
cmp 000101 ..... ..... ..... 000 0000 0001 @typea
cmpu 000101 ..... ..... ..... 000 0000 0011 @typea
+pcmpbf 100000 ..... ..... ..... 100 0000 0000 @typea
+pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea
+pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea
+
rsub 000001 ..... ..... ..... 000 0000 0000 @typea
rsubc 000011 ..... ..... ..... 000 0000 0000 @typea
rsubk 000101 ..... ..... ..... 000 0000 0000 @typea
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index ce91645f05..de2cf5b153 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -279,6 +279,10 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg,
bool side_effects,
static bool trans_##NAME(DisasContext *dc, arg_typea *a) \
{ return do_typea(dc, a, SE, FN); }
+#define DO_TYPEA_CFG(NAME, CFG, SE, FN) \
+ static bool trans_##NAME(DisasContext *dc, arg_typea *a) \
+ { return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); }
+
#define DO_TYPEBI(NAME, SE, FNI) \
static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \
{ return do_typeb_imm(dc, a, SE, FNI); }
@@ -350,6 +354,20 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32
inb)
DO_TYPEA(cmp, false, gen_cmp)
DO_TYPEA(cmpu, false, gen_cmpu)
+static void gen_pcmpeq(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
+{
+ tcg_gen_setcond_i32(TCG_COND_EQ, out, ina, inb);
+}
+
+static void gen_pcmpne(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
+{
+ tcg_gen_setcond_i32(TCG_COND_NE, out, ina, inb);
+}
+
+DO_TYPEA_CFG(pcmpbf, use_pcmp_instr, false, gen_helper_pcmpbf)
+DO_TYPEA_CFG(pcmpeq, use_pcmp_instr, false, gen_pcmpeq)
+DO_TYPEA_CFG(pcmpne, use_pcmp_instr, false, gen_pcmpne)
+
/* No input carry, but output carry. */
static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
@@ -399,49 +417,10 @@ DO_TYPEBV(rsubic, true, gen_rsubc)
DO_TYPEBV(rsubik, false, gen_rsubk)
DO_TYPEBV(rsubikc, true, gen_rsubkc)
-static void dec_pattern(DisasContext *dc)
-{
- unsigned int mode;
-
- if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) {
- return;
- }
-
- mode = dc->opcode & 3;
- switch (mode) {
- case 0:
- /* pcmpbf. */
- if (dc->rd)
- gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
- break;
- case 2:
- if (dc->rd) {
- tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd],
- cpu_R[dc->ra], cpu_R[dc->rb]);
- }
- break;
- case 3:
- if (dc->rd) {
- tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd],
- cpu_R[dc->ra], cpu_R[dc->rb]);
- }
- break;
- default:
- cpu_abort(CPU(dc->cpu),
- "unsupported pattern insn opcode=%x\n", dc->opcode);
- break;
- }
-}
-
static void dec_and(DisasContext *dc)
{
unsigned int not;
- if (!dc->type_b && (dc->imm & (1 << 10))) {
- dec_pattern(dc);
- return;
- }
-
not = dc->opcode & (1 << 1);
if (!dc->rd)
@@ -455,22 +434,12 @@ static void dec_and(DisasContext *dc)
static void dec_or(DisasContext *dc)
{
- if (!dc->type_b && (dc->imm & (1 << 10))) {
- dec_pattern(dc);
- return;
- }
-
if (dc->rd)
tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
}
static void dec_xor(DisasContext *dc)
{
- if (!dc->type_b && (dc->imm & (1 << 10))) {
- dec_pattern(dc);
- return;
- }
-
if (dc->rd)
tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
}
--
2.25.1
- [PATCH 32/77] target/microblaze: Remove empty D macros, (continued)
- [PATCH 32/77] target/microblaze: Remove empty D macros, Richard Henderson, 2020/08/25
- [PATCH 25/77] target/microblaze: Split out MSR[C] to its own variable, Richard Henderson, 2020/08/25
- [PATCH 33/77] target/microblaze: Remove LOG_DIS, Richard Henderson, 2020/08/25
- [PATCH 36/77] target/microblaze: Convert dec_add to decodetree, Richard Henderson, 2020/08/25
- [PATCH 37/77] target/microblaze: Convert dec_sub to decodetree, Richard Henderson, 2020/08/25
- [PATCH 28/77] target/microblaze: Convert to DisasContextBase, Richard Henderson, 2020/08/25
- [PATCH 31/77] target/microblaze: Remove DISAS_GNU, Richard Henderson, 2020/08/25
- [PATCH 34/77] target/microblaze: Ensure imm constant is always available, Richard Henderson, 2020/08/25
- [PATCH 35/77] target/microblaze: Add decodetree infrastructure, Richard Henderson, 2020/08/25
- [PATCH 38/77] target/microblaze: Implement cmp and cmpu inline, Richard Henderson, 2020/08/25
- [PATCH 39/77] target/microblaze: Convert dec_pattern to decodetree,
Richard Henderson <=
- [PATCH 42/77] target/microblaze: Convert dec_div to decodetree, Richard Henderson, 2020/08/25
- [PATCH 40/77] target/microblaze: Convert dec_and, dec_or, dec_xor to decodetree, Richard Henderson, 2020/08/25
- [PATCH 43/77] target/microblaze: Unwind properly when raising divide-by-zero, Richard Henderson, 2020/08/25
- [PATCH 41/77] target/microblaze: Convert dec_mul to decodetree, Richard Henderson, 2020/08/25
- [PATCH 44/77] target/microblaze: Convert dec_bit to decodetree, Richard Henderson, 2020/08/25
- [PATCH 45/77] target/microblaze: Convert dec_barrel to decodetree, Richard Henderson, 2020/08/25
- [PATCH 47/77] target/microblaze: Convert dec_fpu to decodetree, Richard Henderson, 2020/08/25
- [PATCH 46/77] target/microblaze: Convert dec_imm to decodetree, Richard Henderson, 2020/08/25
- [PATCH 48/77] target/microblaze: Fix cpu unwind for fpu exceptions, Richard Henderson, 2020/08/25
- [PATCH 49/77] target/microblaze: Mark fpu helpers TCG_CALL_NO_WG, Richard Henderson, 2020/08/25