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Re: [PATCH v3 13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v3 13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs |
Date: |
Tue, 1 Sep 2020 11:46:57 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 |
On 9/1/20 3:39 AM, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
>
> Microchip PolarFire SoC integrates 2 Candence GEMs to provide
> IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.
>
> On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
> GEM1 connects to a PHY at address 9.
>
> The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we
> must specify 2 '-nic' options from the command line in order to get
> a working ethernet.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v1)
>
> include/hw/riscv/microchip_pfsoc.h | 7 +++++++
> hw/riscv/microchip_pfsoc.c | 39
> ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 46 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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