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[PATCH 2/4] hw/sd/sdhci: Resume pending DMA transfers on MMIO accesses
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 2/4] hw/sd/sdhci: Resume pending DMA transfers on MMIO accesses |
Date: |
Thu, 3 Sep 2020 19:28:04 +0200 |
If we have pending DMA requests scheduled, process them first.
So far we don't need to implement a bottom half to process them.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/sd/sdhci.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 703357e94a7..2b197631870 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -945,11 +945,21 @@ sdhci_buff_access_is_sequential(SDHCIState *s, unsigned
byte_num)
return true;
}
+static void sdhci_resume_pending_transfer(SDHCIState *s)
+{
+ timer_del(s->transfer_timer);
+ sdhci_data_transfer(s);
+}
+
static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
{
SDHCIState *s = (SDHCIState *)opaque;
uint32_t ret = 0;
+ if (timer_pending(s->transfer_timer)) {
+ sdhci_resume_pending_transfer(s);
+ }
+
switch (offset & ~0x3) {
case SDHC_SYSAD:
ret = s->sdmasysad;
@@ -1093,6 +1103,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
uint32_t value = val;
value <<= shift;
+ if (timer_pending(s->transfer_timer)) {
+ sdhci_resume_pending_transfer(s);
+ }
+
switch (offset & ~0x3) {
case SDHC_SYSAD:
s->sdmasysad = (s->sdmasysad & mask) | value;
--
2.26.2
- [PATCH 0/4] hw/sd/sdhci: Strengthen multiple DMA transfers, Philippe Mathieu-Daudé, 2020/09/03
- [PATCH 1/4] hw/sd/sdhci: Stop multiple transfers when block count is cleared, Philippe Mathieu-Daudé, 2020/09/03
- [PATCH 2/4] hw/sd/sdhci: Resume pending DMA transfers on MMIO accesses,
Philippe Mathieu-Daudé <=
- [PATCH 3/4] hw/sd/sdhci: Let sdhci_update_irq() return if IRQ was delivered, Philippe Mathieu-Daudé, 2020/09/03
- [PATCH 4/4] hw/sd/sdhci: Yield if interrupt delivered during multiple transfer, Philippe Mathieu-Daudé, 2020/09/03
- Re: [PATCH 0/4] hw/sd/sdhci: Strengthen multiple DMA transfers, Philippe Mathieu-Daudé, 2020/09/10
- Re: [PATCH 0/4] hw/sd/sdhci: Strengthen multiple DMA transfers, Alexander Bulekov, 2020/09/10
- Re: [PATCH 0/4] hw/sd/sdhci: Strengthen multiple DMA transfers, Philippe Mathieu-Daudé, 2020/09/18