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Re: [PATCH 1/5] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA c
From: |
Richard Henderson |
Subject: |
Re: [PATCH 1/5] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check |
Date: |
Fri, 11 Sep 2020 12:27:06 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 9/10/20 10:38 AM, Peter Maydell wrote:
> The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN
> bit in short-descriptor translation table format descriptors. This
> is indicated by ID_MMFR0.VMSA being at least 0b0100. Replace the
> feature bit with an ID register check, in line with our preference
> for ID register checks over feature bits.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/cpu.h | 15 ++++++++++++++-
> target/arm/cpu.c | 1 -
> target/arm/helper.c | 5 +++--
> 3 files changed, 17 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
- [PATCH 0/5] handle M-profile in fp16_arith isar_feature test, Peter Maydell, 2020/09/10
- [PATCH 2/5] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters, Peter Maydell, 2020/09/10
- [PATCH 1/5] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check, Peter Maydell, 2020/09/10
- Re: [PATCH 1/5] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check,
Richard Henderson <=
- [PATCH 3/5] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs, Peter Maydell, 2020/09/10
- [PATCH 5/5] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile, Peter Maydell, 2020/09/10
- [PATCH 4/5] target/arm: Add ID register values for Cortex-M0, Peter Maydell, 2020/09/10
- Re: [PATCH 0/5] handle M-profile in fp16_arith isar_feature test, Richard Henderson, 2020/09/11