[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PULL 32/36] tests/acceptance: console boot tests for quanta-gsj
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PULL 32/36] tests/acceptance: console boot tests for quanta-gsj |
Date: |
Fri, 18 Sep 2020 15:52:54 +0200 |
Hi Havard,
On Mon, Sep 14, 2020 at 5:47 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> From: Havard Skinnemoen <hskinnemoen@google.com>
>
> This adds two acceptance tests for the quanta-gsj machine.
>
> One test downloads a lightly patched openbmc flash image from github and
> verifies that it boots all the way to the login prompt.
>
> The other test downloads a kernel, initrd and dtb built from the same
> openbmc source and verifies that the kernel detects all CPUs and boots
> to the point where it can't find the root filesystem (because we have no
> flash image in this case).
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
> Message-id: 20200911052101.2602693-15-hskinnemoen@google.com
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
[...]
> + def test_arm_quanta_gsj_initrd(self):
> + """
> + :avocado: tags=arch:arm
> + :avocado: tags=machine:quanta-gsj
> + """
> + initrd_url = (
> + 'https://github.com/hskinnemoen/openbmc/releases/download/'
> + '20200711-gsj-qemu-0/obmc-phosphor-initramfs-gsj.cpio.xz')
> + initrd_hash = '98fefe5d7e56727b1eb17d5c00311b1b5c945300'
> + initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
> + kernel_url = (
> + 'https://github.com/hskinnemoen/openbmc/releases/download/'
> + '20200711-gsj-qemu-0/uImage-gsj.bin')
> + kernel_hash = 'fa67b2f141d56d39b3c54305c0e8a899c99eb2c7'
> + kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
> + dtb_url = (
> + 'https://github.com/hskinnemoen/openbmc/releases/download/'
> + '20200711-gsj-qemu-0/nuvoton-npcm730-gsj.dtb')
> + dtb_hash = '18315f7006d7b688d8312d5c727eecd819aa36a4'
> + dtb_path = self.fetch_asset(dtb_url, asset_hash=dtb_hash)
> +
> + self.vm.set_console()
> + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
> + 'console=ttyS0,115200n8 '
> + 'earlycon=uart8250,mmio32,0xf0001000')
> + self.vm.add_args('-kernel', kernel_path,
> + '-initrd', initrd_path,
> + '-dtb', dtb_path,
> + '-append', kernel_command_line)
> + self.vm.launch()
> +
> + self.wait_for_console_pattern('Booting Linux on physical CPU 0x0')
> + self.wait_for_console_pattern('CPU1: thread -1, cpu 1, socket 0')
> + self.wait_for_console_pattern(
> + 'Give root password for system maintenance')
This test is failing (timeout) on our CI:
https://gitlab.com/philmd/qemu/-/jobs/745483978#L857
- [PULL 25/36] hw/arm: Load -bios image as a boot ROM for npcm7xx, (continued)
- [PULL 25/36] hw/arm: Load -bios image as a boot ROM for npcm7xx, Peter Maydell, 2020/09/14
- [PULL 24/36] roms: Add virtual Boot ROM for NPCM7xx SoCs, Peter Maydell, 2020/09/14
- [PULL 23/36] hw/arm: Add two NPCM7xx-based machines, Peter Maydell, 2020/09/14
- [PULL 27/36] hw/mem: Stubbed out NPCM7xx Memory Controller model, Peter Maydell, 2020/09/14
- [PULL 29/36] hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj, Peter Maydell, 2020/09/14
- [PULL 26/36] hw/nvram: NPCM7xx OTP device model, Peter Maydell, 2020/09/14
- [PULL 30/36] hw/arm/npcm7xx: add board setup stub for CPU and UART clocks, Peter Maydell, 2020/09/14
- [PULL 28/36] hw/ssi: NPCM7xx Flash Interface Unit device model, Peter Maydell, 2020/09/14
- [PULL 31/36] docs/system: Add Nuvoton machine documentation, Peter Maydell, 2020/09/14
- [PULL 32/36] tests/acceptance: console boot tests for quanta-gsj, Peter Maydell, 2020/09/14
- Re: [PULL 32/36] tests/acceptance: console boot tests for quanta-gsj,
Philippe Mathieu-Daudé <=
- [PULL 34/36] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers, Peter Maydell, 2020/09/14
- [PULL 36/36] MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller, Peter Maydell, 2020/09/14
- [PULL 35/36] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller, Peter Maydell, 2020/09/14
- [PULL 33/36] hw/net/can: Introduce Xilinx ZynqMP CAN controller, Peter Maydell, 2020/09/14