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[PATCH v3 02/81] target/arm: Fix sve_zip_p vs odd vector lengths
From: |
Richard Henderson |
Subject: |
[PATCH v3 02/81] target/arm: Fix sve_zip_p vs odd vector lengths |
Date: |
Fri, 18 Sep 2020 11:36:32 -0700 |
Wrote too much with low-half zip (zip1) with vl % 512 != 0.
Adjust all of the x + (y << s) to x | (y << s) as a style fix.
We only ever have exact overlap between D, M, and N. Therefore
we only need a single temporary, and we do not need to check for
partial overlap.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve_helper.c | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index fcb46f150f..b8651ae173 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -1870,6 +1870,7 @@ void HELPER(sve_zip_p)(void *vd, void *vn, void *vm,
uint32_t pred_desc)
intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
intptr_t high = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1);
+ int esize = 1 << esz;
uint64_t *d = vd;
intptr_t i;
@@ -1882,33 +1883,35 @@ void HELPER(sve_zip_p)(void *vd, void *vn, void *vm,
uint32_t pred_desc)
mm = extract64(mm, high * half, half);
nn = expand_bits(nn, esz);
mm = expand_bits(mm, esz);
- d[0] = nn + (mm << (1 << esz));
+ d[0] = nn | (mm << esize);
} else {
- ARMPredicateReg tmp_n, tmp_m;
+ ARMPredicateReg tmp;
/* We produce output faster than we consume input.
Therefore we must be mindful of possible overlap. */
- if ((vn - vd) < (uintptr_t)oprsz) {
- vn = memcpy(&tmp_n, vn, oprsz);
- }
- if ((vm - vd) < (uintptr_t)oprsz) {
- vm = memcpy(&tmp_m, vm, oprsz);
+ if (vd == vn) {
+ vn = memcpy(&tmp, vn, oprsz);
+ if (vd == vm) {
+ vm = vn;
+ }
+ } else if (vd == vm) {
+ vm = memcpy(&tmp, vm, oprsz);
}
if (high) {
high = oprsz >> 1;
}
- if ((high & 3) == 0) {
+ if ((oprsz & 7) == 0) {
uint32_t *n = vn, *m = vm;
high >>= 2;
- for (i = 0; i < DIV_ROUND_UP(oprsz, 8); i++) {
+ for (i = 0; i < oprsz / 8; i++) {
uint64_t nn = n[H4(high + i)];
uint64_t mm = m[H4(high + i)];
nn = expand_bits(nn, esz);
mm = expand_bits(mm, esz);
- d[i] = nn + (mm << (1 << esz));
+ d[i] = nn | (mm << esize);
}
} else {
uint8_t *n = vn, *m = vm;
@@ -1920,7 +1923,7 @@ void HELPER(sve_zip_p)(void *vd, void *vn, void *vm,
uint32_t pred_desc)
nn = expand_bits(nn, esz);
mm = expand_bits(mm, esz);
- d16[H2(i)] = nn + (mm << (1 << esz));
+ d16[H2(i)] = nn | (mm << esize);
}
}
}
--
2.25.1
- [PATCH v3 00/81] target/arm: Implement SVE2, Richard Henderson, 2020/09/18
- [PATCH v3 01/81] target/arm: Fix sve_uzp_p vs odd vector lengths, Richard Henderson, 2020/09/18
- [PATCH v3 02/81] target/arm: Fix sve_zip_p vs odd vector lengths,
Richard Henderson <=
- [PATCH v3 03/81] target/arm: Fix sve_punpk_p vs odd vector lengths, Richard Henderson, 2020/09/18
- [PATCH v3 04/81] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2, Richard Henderson, 2020/09/18
- [PATCH v3 06/81] target/arm: Implement SVE2 integer pairwise add and accumulate long, Richard Henderson, 2020/09/18
- [PATCH v3 05/81] target/arm: Implement SVE2 Integer Multiply - Unpredicated, Richard Henderson, 2020/09/18
- [PATCH v3 07/81] target/arm: Implement SVE2 integer unary operations (predicated), Richard Henderson, 2020/09/18
- [PATCH v3 08/81] target/arm: Split out saturating/rounding shifts from neon, Richard Henderson, 2020/09/18
- [PATCH v3 11/81] target/arm: Implement SVE2 integer pairwise arithmetic, Richard Henderson, 2020/09/18
- [PATCH v3 09/81] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated), Richard Henderson, 2020/09/18
- [PATCH v3 10/81] target/arm: Implement SVE2 integer halving add/subtract (predicated), Richard Henderson, 2020/09/18
- [PATCH v3 13/81] target/arm: Implement SVE2 integer add/subtract long, Richard Henderson, 2020/09/18