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[PATCH v3 69/81] target/arm: Implement SVE2 crypto constructive binary o
From: |
Richard Henderson |
Subject: |
[PATCH v3 69/81] target/arm: Implement SVE2 crypto constructive binary operations |
Date: |
Fri, 18 Sep 2020 11:37:39 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 5 +++++
target/arm/sve.decode | 4 ++++
target/arm/translate-sve.c | 16 ++++++++++++++++
3 files changed, 25 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f5052a58a4..67b2834035 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3917,6 +3917,11 @@ static inline bool isar_feature_aa64_sve2_bitperm(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
}
+static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
+}
+
static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 2ebf65f376..5f2fad4754 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1564,3 +1564,7 @@ AESMC 01000101 00 10000011100 decrypt:1 00000
rd:5
AESE 01000101 00 10001 0 11100 0 ..... ..... @rdn_rm_e0
AESD 01000101 00 10001 0 11100 1 ..... ..... @rdn_rm_e0
SM4E 01000101 00 10001 1 11100 0 ..... ..... @rdn_rm_e0
+
+# SVE2 crypto constructive binary operations
+SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0
+RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index aa459ed30a..cb493d838d 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -8176,3 +8176,19 @@ static bool trans_SM4E(DisasContext *s, arg_rrr_esz *a)
{
return do_sm4(s, a, gen_helper_crypto_sm4e);
}
+
+static bool trans_SM4EKEY(DisasContext *s, arg_rrr_esz *a)
+{
+ return do_sm4(s, a, gen_helper_crypto_sm4ekey);
+}
+
+static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sha3, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm);
+ }
+ return true;
+}
--
2.25.1
- [PATCH v3 65/81] target/arm: Implement SVE mixed sign dot product (indexed), (continued)
- [PATCH v3 65/81] target/arm: Implement SVE mixed sign dot product (indexed), Richard Henderson, 2020/09/18
- [PATCH v3 64/81] target/arm: Implement SVE2 complex integer multiply-add (indexed), Richard Henderson, 2020/09/18
- [PATCH v3 67/81] target/arm: Implement SVE2 crypto unary operations, Richard Henderson, 2020/09/18
- [PATCH v3 70/81] target/arm: Implement SVE2 TBL, TBX, Richard Henderson, 2020/09/18
- [PATCH v3 44/81] target/arm: Implement SVE2 RSUBHNB, RSUBHNT, Richard Henderson, 2020/09/18
- [PATCH v3 54/81] target/arm: Split out formats for 3 vectors + 1 index, Richard Henderson, 2020/09/18
- [PATCH v3 57/81] target/arm: Implement SVE2 saturating multiply-add high (indexed), Richard Henderson, 2020/09/18
- [PATCH v3 62/81] target/arm: Implement SVE2 saturating multiply high (indexed), Richard Henderson, 2020/09/18
- [PATCH v3 58/81] target/arm: Implement SVE2 saturating multiply-add (indexed), Richard Henderson, 2020/09/18
- [PATCH v3 61/81] target/arm: Implement SVE2 signed saturating doubling multiply high, Richard Henderson, 2020/09/18
- [PATCH v3 69/81] target/arm: Implement SVE2 crypto constructive binary operations,
Richard Henderson <=
- [PATCH v3 73/81] target/arm: Implement SVE2 FCVTXNT, FCVTX, Richard Henderson, 2020/09/18
- [PATCH v3 68/81] target/arm: Implement SVE2 crypto destructive binary operations, Richard Henderson, 2020/09/18
- [PATCH v3 77/81] target/arm: Implement 128-bit ZIP, UZP, TRN, Richard Henderson, 2020/09/18
- [PATCH v3 66/81] target/arm: Implement SVE mixed sign dot product, Richard Henderson, 2020/09/18
- [PATCH v3 71/81] target/arm: Implement SVE2 FCVTNT, Richard Henderson, 2020/09/18
- [PATCH v3 74/81] target/arm: Implement SVE2 FLOGB, Richard Henderson, 2020/09/18
- [PATCH v3 72/81] target/arm: Implement SVE2 FCVTLT, Richard Henderson, 2020/09/18
- [PATCH v3 75/81] target/arm: Share table of sve load functions, Richard Henderson, 2020/09/18
- [PATCH v3 76/81] target/arm: Implement SVE2 LD1RO, Richard Henderson, 2020/09/18
- [PATCH v3 79/81] target/arm: Implement SVE2 fp multiply-add long, Richard Henderson, 2020/09/18