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[PATCH 11/16] hw/mips/cps: Expose input clock and connect it to CPU core
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 11/16] hw/mips/cps: Expose input clock and connect it to CPU cores |
Date: |
Mon, 28 Sep 2020 19:15:34 +0200 |
Expose a qdev input clock named 'clk', and connect it to each
core.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/mips/cps.h | 2 ++
hw/mips/cps.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
index 9e35a881366..859a8d4a674 100644
--- a/include/hw/mips/cps.h
+++ b/include/hw/mips/cps.h
@@ -21,6 +21,7 @@
#define MIPS_CPS_H
#include "hw/sysbus.h"
+#include "hw/clock.h"
#include "hw/misc/mips_cmgcr.h"
#include "hw/intc/mips_gic.h"
#include "hw/misc/mips_cpc.h"
@@ -43,6 +44,7 @@ struct MIPSCPSState {
MIPSGICState gic;
MIPSCPCState cpc;
MIPSITUState itu;
+ Clock *clock;
};
qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 23c0f87e41a..c332609f7b3 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -22,6 +22,7 @@
#include "qemu/module.h"
#include "hw/mips/cps.h"
#include "hw/mips/mips.h"
+#include "hw/qdev-clock.h"
#include "hw/qdev-properties.h"
#include "hw/mips/cpudevs.h"
#include "sysemu/kvm.h"
@@ -38,6 +39,7 @@ static void mips_cps_init(Object *obj)
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
MIPSCPSState *s = MIPS_CPS(obj);
+ s->clock = qdev_init_clock_in(DEVICE(obj), "clk", NULL, NULL);
/*
* Cover entire address space as there do not seem to be any
* constraints for the base address of CPC and GIC.
@@ -80,6 +82,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
errp)) {
return;
}
+ qdev_connect_clock_in(DEVICE(cpu), "clk", s->clock);
if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) {
return;
--
2.26.2
- Re: [PATCH 01/16] hw/core/cpu: Let CPU object have a clock source, (continued)
- [PATCH 09/16] hw/mips/mipssim: Correct CPU frequency, Philippe Mathieu-Daudé, 2020/09/28
- [PATCH 02/16] target/mips: Move cpu_mips_get_random() with CP0 helpers, Philippe Mathieu-Daudé, 2020/09/28
- [PATCH 03/16] target/mips/cp0_timer: Explicit unit in variable name, Philippe Mathieu-Daudé, 2020/09/28
- [PATCH 08/16] hw/mips/fuloong2e: Set CPU frequency to 533 MHz, Philippe Mathieu-Daudé, 2020/09/28
- [PATCH 06/16] target/mips: Keep CP0 counter in sync with the CPU frequency, Philippe Mathieu-Daudé, 2020/09/28
- [PATCH 07/16] hw/mips/r4k: Explicit CPU frequency is 200 MHz, Philippe Mathieu-Daudé, 2020/09/28
- [PATCH 12/16] hw/mips/boston: Set CPU frequency to 1 GHz, Philippe Mathieu-Daudé, 2020/09/28
- [PATCH 13/16] hw/mips/malta: Set CPU frequency to 320 MHz, Philippe Mathieu-Daudé, 2020/09/28
- [PATCH 10/16] hw/mips/jazz: Correct CPU frequencies, Philippe Mathieu-Daudé, 2020/09/28
- [PATCH 11/16] hw/mips/cps: Expose input clock and connect it to CPU cores,
Philippe Mathieu-Daudé <=
- [PATCH 14/16] hw/mips/cps: Do not allow use without input clock, Philippe Mathieu-Daudé, 2020/09/28
- [PATCH 15/16] target/mips/cpu: Do not allow system-mode use without input clock, Philippe Mathieu-Daudé, 2020/09/28
- [PATCH 16/16] tests/acceptance: Test the MIPSsim machine, Philippe Mathieu-Daudé, 2020/09/28