[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC v5 41/68] target/riscv: rvv-1.0: single-width bit shift instruction
From: |
frank . chang |
Subject: |
[RFC v5 41/68] target/riscv: rvv-1.0: single-width bit shift instructions |
Date: |
Wed, 30 Sep 2020 03:04:16 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index cce1712af0..20b104527c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1932,9 +1932,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
-GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli)
-GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri)
-GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari)
+GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli)
+GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri)
+GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
--
2.17.1
- [RFC v5 30/68] target/riscv: rvv-1.0: set-X-first mask bit instructions, (continued)
- [RFC v5 30/68] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/09/29
- [RFC v5 31/68] target/riscv: rvv-1.0: iota instruction, frank . chang, 2020/09/29
- [RFC v5 32/68] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/09/29
- [RFC v5 33/68] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2020/09/29
- [RFC v5 34/68] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2020/09/29
- [RFC v5 35/68] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2020/09/29
- [RFC v5 36/68] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/09/29
- [RFC v5 37/68] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2020/09/29
- [RFC v5 38/68] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2020/09/29
- [RFC v5 40/68] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2020/09/29
- [RFC v5 41/68] target/riscv: rvv-1.0: single-width bit shift instructions,
frank . chang <=
- [RFC v5 39/68] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2020/09/29
- [RFC v5 42/68] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/09/29
- [RFC v5 43/68] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2020/09/29
- [RFC v5 44/68] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2020/09/29
- [RFC v5 45/68] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2020/09/29
- [RFC v5 46/68] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2020/09/29
- [RFC v5 47/68] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2020/09/29
- [RFC v5 48/68] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2020/09/29
- [RFC v5 49/68] target/riscv: rvv-1.0: slide instructions, frank . chang, 2020/09/29
- [RFC v5 51/68] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2020/09/29