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[PATCH v3 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH
From: |
Richard Henderson |
Subject: |
[PATCH v3 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH |
Date: |
Mon, 11 Jan 2021 09:00:58 -1000 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9cc6a9f83d..ba68d4d7f4 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6883,7 +6883,7 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop)
addr = load_reg(s, a->rn);
tmp = load_reg(s, a->rt);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop);
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN);
disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite);
tcg_temp_free_i32(tmp);
@@ -7039,7 +7039,7 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop)
addr = load_reg(s, a->rn);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop);
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN);
disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel);
tcg_temp_free_i32(addr);
--
2.25.1
- [PATCH v3 03/30] target/arm: Rename TBFLAG_ANY, PSTATE_SS, (continued)
- [PATCH v3 03/30] target/arm: Rename TBFLAG_ANY, PSTATE_SS, Richard Henderson, 2021/01/11
- [PATCH v3 04/30] target/arm: Add wrapper macros for accessing tbflags, Richard Henderson, 2021/01/11
- [PATCH v3 05/30] target/arm: Introduce CPUARMTBFlags, Richard Henderson, 2021/01/11
- [PATCH v3 06/30] target/arm: Move mode specific TB flags to tb->cs_base, Richard Henderson, 2021/01/11
- [PATCH v3 07/30] target/arm: Move TBFLAG_AM32 bits to the top, Richard Henderson, 2021/01/11
- [PATCH v3 08/30] target/arm: Move TBFLAG_ANY bits to the bottom, Richard Henderson, 2021/01/11
- [PATCH v3 09/30] target/arm: Add ALIGN_MEM to TBFLAG_ANY, Richard Henderson, 2021/01/11
- [PATCH v3 12/30] target/arm: Fix SCTLR_B test for TCGv_i64 load/store, Richard Henderson, 2021/01/11
- [PATCH v3 13/30] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness, Richard Henderson, 2021/01/11
- [PATCH v3 11/30] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64, Richard Henderson, 2021/01/11
- [PATCH v3 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH,
Richard Henderson <=
- [PATCH v3 21/30] target/arm: Enforce alignment for VLDn (all lanes), Richard Henderson, 2021/01/11
- [PATCH v3 14/30] target/arm: Enforce word alignment for LDRD/STRD, Richard Henderson, 2021/01/11
- [PATCH v3 10/30] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness, Richard Henderson, 2021/01/11
- [PATCH v3 17/30] target/arm: Enforce alignment for RFE, Richard Henderson, 2021/01/11
- [PATCH v3 24/30] target/arm: Use finalize_memop for aa64 gpr load/store, Richard Henderson, 2021/01/11
- [PATCH v3 26/30] target/arm: Enforce alignment for aa64 load-acq/store-rel, Richard Henderson, 2021/01/11
- [PATCH v3 19/30] target/arm: Enforce alignment for VLDM/VSTM, Richard Henderson, 2021/01/11
- [PATCH v3 27/30] target/arm: Use MemOp for size + endian in aa64 vector ld/st, Richard Henderson, 2021/01/11
- [PATCH v3 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (single), Richard Henderson, 2021/01/11
- [PATCH v3 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple), Richard Henderson, 2021/01/11