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[PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing
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From: |
frank . chang |
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Subject: |
[PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs |
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Date: |
Tue, 12 Jan 2021 17:39:41 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/csr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 28c1ce7928a..176010674e8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -301,7 +301,7 @@ static int write_vxrm(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return -1;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | MSTATUS_SD;
#endif
env->vxrm = val;
@@ -320,7 +320,7 @@ static int write_vxsat(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return -1;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | MSTATUS_SD;
#endif
env->vxsat = val;
@@ -339,7 +339,7 @@ static int write_vstart(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return -1;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | MSTATUS_SD;
#endif
/*
@@ -362,7 +362,7 @@ static int write_vcsr(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return -1;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | MSTATUS_SD;
#endif
env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
--
2.17.1
- [PATCH v6 57/72] target/riscv: rvv-1.0: remove integer extract instruction, (continued)
- [PATCH v6 57/72] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2021/01/12
- [PATCH v6 58/72] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/01/12
- [PATCH v6 60/72] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/01/12
- [PATCH v6 61/72] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/01/12
- [PATCH v6 59/72] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/01/12
- [PATCH v6 62/72] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/01/12
- [PATCH v6 63/72] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/01/12
- [PATCH v6 64/72] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/01/12
- [PATCH v6 65/72] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/01/12
- [PATCH v6 66/72] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/01/12
- [PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs,
frank . chang <=
- [PATCH v6 68/72] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2021/01/12
- [PATCH v6 69/72] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/01/12
- [PATCH v6 70/72] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/01/12
- [PATCH v6 71/72] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/01/12
- [PATCH v6 72/72] target/riscv: set mstatus.SD bit when writing fp CSRs, frank . chang, 2021/01/12
- Re: [PATCH v6 00/72] support vector extension v1.0, no-reply, 2021/01/12
- Re: [PATCH v6 00/72] support vector extension v1.0, Alistair Francis, 2021/01/19