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[PULL 08/21] target/arm: add aarch32 ID register fields to cpu.h
From: |
Peter Maydell |
Subject: |
[PULL 08/21] target/arm: add aarch32 ID register fields to cpu.h |
Date: |
Tue, 12 Jan 2021 16:57:37 +0000 |
From: Leif Lindholm <leif@nuviainc.com>
Add entries present in ARM DDI 0487F.c (August 2020).
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-7-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d8fb8c845ca..f3bca73d987 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1830,6 +1830,8 @@ FIELD(ID_ISAR6, DP, 4, 4)
FIELD(ID_ISAR6, FHM, 8, 4)
FIELD(ID_ISAR6, SB, 12, 4)
FIELD(ID_ISAR6, SPECRES, 16, 4)
+FIELD(ID_ISAR6, BF16, 20, 4)
+FIELD(ID_ISAR6, I8MM, 24, 4)
FIELD(ID_MMFR0, VMSA, 0, 4)
FIELD(ID_MMFR0, PMSA, 4, 4)
@@ -1840,6 +1842,24 @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
FIELD(ID_MMFR0, FCSE, 24, 4)
FIELD(ID_MMFR0, INNERSHR, 28, 4)
+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
+FIELD(ID_MMFR1, L1UNISW, 12, 4)
+FIELD(ID_MMFR1, L1HVD, 16, 4)
+FIELD(ID_MMFR1, L1UNI, 20, 4)
+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
+FIELD(ID_MMFR1, BPRED, 28, 4)
+
+FIELD(ID_MMFR2, L1HVDFG, 0, 4)
+FIELD(ID_MMFR2, L1HVDBG, 4, 4)
+FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
+FIELD(ID_MMFR2, HVDTLB, 12, 4)
+FIELD(ID_MMFR2, UNITLB, 16, 4)
+FIELD(ID_MMFR2, MEMBARR, 20, 4)
+FIELD(ID_MMFR2, WFISTALL, 24, 4)
+FIELD(ID_MMFR2, HWACCFLG, 28, 4)
+
FIELD(ID_MMFR3, CMAINTVA, 0, 4)
FIELD(ID_MMFR3, CMAINTSW, 4, 4)
FIELD(ID_MMFR3, BPMAINT, 8, 4)
@@ -1858,6 +1878,8 @@ FIELD(ID_MMFR4, LSM, 20, 4)
FIELD(ID_MMFR4, CCIDX, 24, 4)
FIELD(ID_MMFR4, EVT, 28, 4)
+FIELD(ID_MMFR5, ETS, 0, 4)
+
FIELD(ID_PFR0, STATE0, 0, 4)
FIELD(ID_PFR0, STATE1, 4, 4)
FIELD(ID_PFR0, STATE2, 8, 4)
@@ -1876,6 +1898,10 @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
FIELD(ID_PFR1, GIC, 28, 4)
+FIELD(ID_PFR2, CSV3, 0, 4)
+FIELD(ID_PFR2, SSBS, 4, 4)
+FIELD(ID_PFR2, RAS_FRAC, 8, 4)
+
FIELD(ID_AA64ISAR0, AES, 4, 4)
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
@@ -1990,6 +2016,8 @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
FIELD(ID_DFR0, PERFMON, 24, 4)
FIELD(ID_DFR0, TRACEFILT, 28, 4)
+FIELD(ID_DFR1, MTPMU, 0, 4)
+
FIELD(DBGDIDR, SE_IMP, 12, 1)
FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
FIELD(DBGDIDR, VERSION, 16, 4)
--
2.20.1
- [PULL 00/21] target-arm queue, Peter Maydell, 2021/01/12
- [PULL 02/21] target/arm: enable Small Translation tables in max CPU, Peter Maydell, 2021/01/12
- [PULL 01/21] target/arm: ARMv8.4-TTST extension, Peter Maydell, 2021/01/12
- [PULL 03/21] target/arm: fix typo in cpu.h ID_AA64PFR1 field name, Peter Maydell, 2021/01/12
- [PULL 04/21] target/arm: make ARMCPU.clidr 64-bit, Peter Maydell, 2021/01/12
- [PULL 05/21] target/arm: make ARMCPU.ctr 64-bit, Peter Maydell, 2021/01/12
- [PULL 06/21] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h, Peter Maydell, 2021/01/12
- [PULL 07/21] target/arm: add aarch64 ID register fields to cpu.h, Peter Maydell, 2021/01/12
- [PULL 08/21] target/arm: add aarch32 ID register fields to cpu.h,
Peter Maydell <=
- [PULL 10/21] docs: Add qemu-storage-daemon(1) manpage to meson.build, Peter Maydell, 2021/01/12
- [PULL 12/21] target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns, Peter Maydell, 2021/01/12
- [PULL 13/21] hw/net/lan9118: Fix RX Status FIFO PEEK value, Peter Maydell, 2021/01/12
- [PULL 11/21] docs: Build and install all the docs in a single manual, Peter Maydell, 2021/01/12
- [PULL 09/21] ui/cocoa: Update path to docs in build tree, Peter Maydell, 2021/01/12
- [PULL 14/21] hw/net/lan9118: Add symbolic constants for register offsets, Peter Maydell, 2021/01/12
- [PULL 16/21] hw/timer: Refactor NPCM7XX Timer to use CLK clock, Peter Maydell, 2021/01/12
- [PULL 15/21] hw/misc: Add clock converter in NPCM7XX CLK module, Peter Maydell, 2021/01/12
- [PULL 18/21] hw/misc: Add a PWM module for NPCM7XX, Peter Maydell, 2021/01/12