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[PATCH v3 02/12] hw/block/nvme: fix 64 bit register hi/lo split writes
From: |
Klaus Jensen |
Subject: |
[PATCH v3 02/12] hw/block/nvme: fix 64 bit register hi/lo split writes |
Date: |
Tue, 19 Jan 2021 11:14:54 +0100 |
From: Klaus Jensen <k.jensen@samsung.com>
64 bit registers like ASQ and ACQ should be writable by both a hi/lo 32
bit write combination as well as a plain 64 bit write. The spec does not
define ordering on the hi/lo split, but the code currently assumes that
the low order bits are written first. Additionally, the code does not
consider that another address might already have been written into the
register, causing the OR'ing to result in a bad address.
Fix this by explicitly overwriting only the low or high order bits for
32 bit writes.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index c1211b298603..9a508df8d200 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -3790,19 +3790,21 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset,
uint64_t data,
trace_pci_nvme_mmio_aqattr(data & 0xffffffff);
break;
case 0x28: /* ASQ */
- n->bar.asq = data;
+ n->bar.asq = size == 8 ? data :
+ (n->bar.asq & ~0xffffffffULL) | (data & 0xffffffff);
trace_pci_nvme_mmio_asqaddr(data);
break;
case 0x2c: /* ASQ hi */
- n->bar.asq |= data << 32;
+ n->bar.asq = (n->bar.asq & 0xffffffff) | (data << 32);
trace_pci_nvme_mmio_asqaddr_hi(data, n->bar.asq);
break;
case 0x30: /* ACQ */
trace_pci_nvme_mmio_acqaddr(data);
- n->bar.acq = data;
+ n->bar.acq = size == 8 ? data :
+ (n->bar.acq & ~0xffffffffULL) | (data & 0xffffffff);
break;
case 0x34: /* ACQ hi */
- n->bar.acq |= data << 32;
+ n->bar.acq = (n->bar.acq & 0xffffffff) | (data << 32);
trace_pci_nvme_mmio_acqaddr_hi(data, n->bar.acq);
break;
case 0x38: /* CMBLOC */
--
2.30.0
- [PATCH v3 00/12] hw/block/nvme: misc cmb/pmr patches and bump to v1.4, Klaus Jensen, 2021/01/19
- [PATCH v3 02/12] hw/block/nvme: fix 64 bit register hi/lo split writes,
Klaus Jensen <=
- [PATCH v3 01/12] hw/block/nvme: add size to mmio read/write trace events, Klaus Jensen, 2021/01/19
- [PATCH v3 03/12] hw/block/nvme: indicate CMB support through controller capabilities register, Klaus Jensen, 2021/01/19
- [PATCH v3 04/12] hw/block/nvme: move msix table and pba to BAR 0, Klaus Jensen, 2021/01/19
- [PATCH v3 05/12] hw/block/nvme: allow cmb and pmr to coexist, Klaus Jensen, 2021/01/19
- [PATCH v3 06/12] hw/block/nvme: rename PMR/CMB shift/mask fields, Klaus Jensen, 2021/01/19
- [PATCH v3 07/12] hw/block/nvme: remove redundant zeroing of PMR registers, Klaus Jensen, 2021/01/19
- [PATCH v3 08/12] hw/block/nvme: disable PMR at boot up, Klaus Jensen, 2021/01/19
- [PATCH v3 09/12] hw/block/nvme: add PMR RDS/WDS support, Klaus Jensen, 2021/01/19
- [PATCH v3 10/12] hw/block/nvme: move cmb logic to v1.4, Klaus Jensen, 2021/01/19