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[PULL 23/33] target/arm: Introduce PREDDESC field definitions
From: |
Peter Maydell |
Subject: |
[PULL 23/33] target/arm: Introduce PREDDESC field definitions |
Date: |
Tue, 19 Jan 2021 15:10:54 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
SVE predicate operations cannot use the "usual" simd_desc
encoding, because the lengths are not a multiple of 8.
But we were abusing the SIMD_* fields to store values anyway.
This abuse broke when SIMD_OPRSZ_BITS was modified in e2e7168a214.
Introduce a new set of field definitions for exclusive use
of predicates, so that it is obvious what kind of predicate
we are manipulating. To be used in future patches.
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210113062650.593824-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 27cc93f15ac..853fa88fd61 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1348,6 +1348,15 @@ void arm_log_exception(int idx);
#define LOG2_TAG_GRANULE 4
#define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
+/*
+ * SVE predicates are 1/8 the size of SVE vectors, and cannot use
+ * the same simd_desc() encoding due to restrictions on size.
+ * Use these instead.
+ */
+FIELD(PREDDESC, OPRSZ, 0, 6)
+FIELD(PREDDESC, ESZ, 6, 2)
+FIELD(PREDDESC, DATA, 8, 24)
+
/*
* The SVE simd_data field, for memory ops, contains either
* rd (5 bits) or a shift count (2 bits).
--
2.20.1
- [PULL 15/33] target/arm: translate NS bit in page-walks, (continued)
- [PULL 15/33] target/arm: translate NS bit in page-walks, Peter Maydell, 2021/01/19
- [PULL 12/33] target/arm: add ARMv8.4-SEL2 system registers, Peter Maydell, 2021/01/19
- [PULL 17/33] target/arm: secure stage 2 translation regime, Peter Maydell, 2021/01/19
- [PULL 21/33] target/arm: enable Secure EL2 in max CPU, Peter Maydell, 2021/01/19
- [PULL 14/33] target/arm: do S1_ptw_translate() before address space lookup, Peter Maydell, 2021/01/19
- [PULL 16/33] target/arm: generalize 2-stage page-walk condition, Peter Maydell, 2021/01/19
- [PULL 18/33] target/arm: set HPFAR_EL2.NS on secure stage 2 faults, Peter Maydell, 2021/01/19
- [PULL 22/33] target/arm: refactor vae1_tlbmask(), Peter Maydell, 2021/01/19
- [PULL 24/33] target/arm: Update PFIRST, PNEXT for pred_desc, Peter Maydell, 2021/01/19
- [PULL 25/33] target/arm: Update ZIP, UZP, TRN for pred_desc, Peter Maydell, 2021/01/19
- [PULL 23/33] target/arm: Introduce PREDDESC field definitions,
Peter Maydell <=
- [PULL 20/33] target/arm: Implement SCR_EL2.EEL2, Peter Maydell, 2021/01/19
- [PULL 19/33] target/arm: revector to run-time pick target EL, Peter Maydell, 2021/01/19
- [PULL 27/33] hw/misc/pvpanic: split-out generic and bus dependent code, Peter Maydell, 2021/01/19
- [PULL 28/33] hw/misc/pvpanic: add PCI interface support, Peter Maydell, 2021/01/19
- [PULL 26/33] target/arm: Update REV, PUNPK for pred_desc, Peter Maydell, 2021/01/19
- [PULL 29/33] pvpanic : update pvpanic spec document, Peter Maydell, 2021/01/19
- [PULL 33/33] docs: Build and install all the docs in a single manual, Peter Maydell, 2021/01/19
- [PULL 32/33] target/arm/m_helper: Silence GCC 10 maybe-uninitialized error, Peter Maydell, 2021/01/19
- [PULL 31/33] npcm7xx_adc-test: Fix memleak in adc_qom_set, Peter Maydell, 2021/01/19
- [PULL 30/33] tests/qtest: add a test case for pvpanic-pci, Peter Maydell, 2021/01/19