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Re: [PATCH v7 07/35] Hexagon (target/hexagon) scalar core helpers
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v7 07/35] Hexagon (target/hexagon) scalar core helpers |
Date: |
Fri, 22 Jan 2021 21:30:29 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 |
Hi Taylor,
On 1/20/21 4:28 AM, Taylor Simpson wrote:
> The majority of helpers are generated. Define the helper functions needed
> then include the generated file
>
> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
> ---
> target/hexagon/helper.h | 85 ++++
> target/hexagon/op_helper.c | 1066
> ++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 1151 insertions(+)
> create mode 100644 target/hexagon/helper.h
> create mode 100644 target/hexagon/op_helper.c
...
> diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
> new file mode 100644
> index 0000000..5186dd1
> --- /dev/null
> +++ b/target/hexagon/op_helper.c
> @@ -0,0 +1,1066 @@
> +/*
> + * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu.h"
> +#include "exec/helper-proto.h"
> +#include "fpu/softfloat.h"
> +#include "cpu.h"
> +#include "internal.h"
> +#include "macros.h"
> +#include "arch.h"
> +#include "hex_arch_types.h"
> +#include "fma_emu.h"
> +#include "conv_emu.h"
> +
> +#define SF_BIAS 127
> +#define SF_MANTBITS 23
> +
> +/* Exceptions processing helpers */
> +static void QEMU_NORETURN do_raise_exception_err(CPUHexagonState *env,
> + uint32_t exception,
> + uintptr_t pc)
> +{
> + CPUState *cs = CPU(hexagon_env_get_cpu(env));
> + qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception);
> + cs->exception_index = exception;
> + cpu_loop_exit_restore(cs, pc);
> +}
> +
> +void QEMU_NORETURN HELPER(raise_exception)(CPUHexagonState *env, uint32_t
> excp)
> +{
> + do_raise_exception_err(env, excp, 0);
> +}
> +
> +static inline void log_reg_write(CPUHexagonState *env, int rnum,
> + target_ulong val, uint32_t slot)
> +{
> + HEX_DEBUG_LOG("log_reg_write[%d] = " TARGET_FMT_ld " (0x" TARGET_FMT_lx
> ")",
> + rnum, val, val);
> + if (env->slot_cancelled & (1 << slot)) {
> + HEX_DEBUG_LOG(" CANCELLED");
> + }
> + if (val == env->gpr[rnum]) {
> + HEX_DEBUG_LOG(" NO CHANGE");
> + }
> + HEX_DEBUG_LOG("\n");
> + if (!(env->slot_cancelled & (1 << slot))) {
> + env->new_value[rnum] = val;
> +#if HEX_DEBUG
> + /* Do this so HELPER(debug_commit_end) will know */
> + env->reg_written[rnum] = 1;
> +#endif
> + }
> +}
> +
> +static __attribute__((unused))
> +inline void log_reg_write_pair(CPUHexagonState *env, int rnum,
> + int64_t val, uint32_t slot)
> +{
> + HEX_DEBUG_LOG("log_reg_write_pair[%d:%d] = %ld\n", rnum + 1, rnum, val);
> + log_reg_write(env, rnum, val & 0xFFFFFFFF, slot);
> + log_reg_write(env, rnum + 1, (val >> 32) & 0xFFFFFFFF, slot);
> +}
> +
> +static inline void log_pred_write(CPUHexagonState *env, int pnum,
> + target_ulong val)
> +{
> + HEX_DEBUG_LOG("log_pred_write[%d] = " TARGET_FMT_ld
> + " (0x" TARGET_FMT_lx ")\n",
> + pnum, val, val);
> +
> + /* Multiple writes to the same preg are and'ed together */
> + if (env->pred_written & (1 << pnum)) {
> + env->new_pred_value[pnum] &= val & 0xff;
> + } else {
> + env->new_pred_value[pnum] = val & 0xff;
> + env->pred_written |= 1 << pnum;
> + }
> +}
> +
> +static inline void log_store32(CPUHexagonState *env, target_ulong addr,
> + target_ulong val, int width, int slot)
> +{
> + HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", " TARGET_FMT_ld
> + " [0x" TARGET_FMT_lx "])\n",
> + width, addr, val, val);
> + env->mem_log_stores[slot].va = addr;
> + env->mem_log_stores[slot].width = width;
> + env->mem_log_stores[slot].data32 = val;
> +}
> +
> +static inline void log_store64(CPUHexagonState *env, target_ulong addr,
> + int64_t val, int width, int slot)
> +{
> + HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", %ld [0x%lx])\n",
> + width, addr, val, val);
> + env->mem_log_stores[slot].va = addr;
> + env->mem_log_stores[slot].width = width;
> + env->mem_log_stores[slot].data64 = val;
> +}
> +
> +static inline void write_new_pc(CPUHexagonState *env, target_ulong addr)
> +{
> + HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr);
> +
> + /*
> + * If more than one branch is taken in a packet, only the first one
> + * is actually done.
> + */
> + if (env->branch_taken) {
> + HEX_DEBUG_LOG("INFO: multiple branches taken in same packet, "
> + "ignoring the second one\n");
> + } else {
> + fCHECK_PCALIGN(addr);
> + env->branch_taken = 1;
> + env->next_PC = addr;
> + }
> +}
I'm getting:
In file included from ../target/hexagon/op_helper.c:23:
../target/hexagon/op_helper.c: In function ‘log_reg_write_pair’:
../target/hexagon/op_helper.c:74:19: error: format ‘%ld’ expects
argument of type ‘long int’, but argument 4 has type ‘int64_t’ {aka
‘long long int’} [-Werror=format=]
74 | HEX_DEBUG_LOG("log_reg_write_pair[%d:%d] = %ld\n", rnum + 1,
rnum, val);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~
|
|
|
int64_t {aka long long int}
../target/hexagon/internal.h:28:22: note: in definition of macro
‘HEX_DEBUG_LOG’
28 | qemu_log(__VA_ARGS__); \
| ^~~~~~~~~~~
../target/hexagon/op_helper.c:74:50: note: format string is defined here
74 | HEX_DEBUG_LOG("log_reg_write_pair[%d:%d] = %ld\n", rnum + 1,
rnum, val);
| ~~^
| |
| long int
| %lld
In file included from ../target/hexagon/op_helper.c:23:
../target/hexagon/op_helper.c: In function ‘log_store64’:
../target/hexagon/op_helper.c:109:19: error: format ‘%ld’ expects
argument of type ‘long int’, but argument 4 has type ‘int64_t’ {aka
‘long long int’} [-Werror=format=]
109 | HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", %ld [0x%lx])\n",
| ^~~~~~~~~~~~~~~~
110 | width, addr, val, val);
| ~~~
| |
| int64_t {aka long long int}
../target/hexagon/internal.h:28:22: note: in definition of macro
‘HEX_DEBUG_LOG’
28 | qemu_log(__VA_ARGS__); \
| ^~~~~~~~~~~
../target/hexagon/op_helper.c:109:19: error: format ‘%lx’ expects
argument of type ‘long unsigned int’, but argument 5 has type ‘int64_t’
{aka ‘long long int’} [-Werror=format=]
109 | HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", %ld [0x%lx])\n",
| ^~~~~~~~~~~~~~~~
110 | width, addr, val, val);
| ~~~
| |
| int64_t {aka long long int}
../target/hexagon/internal.h:28:22: note: in definition of macro
‘HEX_DEBUG_LOG’
28 | qemu_log(__VA_ARGS__); \
| ^~~~~~~~~~~
../target/hexagon/op_helper.c: In function ‘print_store’:
../target/hexagon/op_helper.c:201:27: error: format ‘%lu’ expects
argument of type ‘long unsigned int’, but argument 3 has type ‘uint64_t’
{aka ‘long long unsigned int’} [-Werror=format=]
201 | HEX_DEBUG_LOG("\tmemd[0x" TARGET_FMT_lx "] = %lu
(0x%016lx)\n",
| ^~~~~~~~~~~
202 | env->mem_log_stores[slot].va,
203 | env->mem_log_stores[slot].data64,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| uint64_t {aka
long long unsigned int}
../target/hexagon/internal.h:28:22: note: in definition of macro
‘HEX_DEBUG_LOG’
28 | qemu_log(__VA_ARGS__); \
| ^~~~~~~~~~~
../target/hexagon/op_helper.c:201:27: error: format ‘%lx’ expects
argument of type ‘long unsigned int’, but argument 4 has type ‘uint64_t’
{aka ‘long long unsigned int’} [-Werror=format=]
201 | HEX_DEBUG_LOG("\tmemd[0x" TARGET_FMT_lx "] = %lu
(0x%016lx)\n",
| ^~~~~~~~~~~
......
204 | env->mem_log_stores[slot].data64);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| uint64_t {aka
long long unsigned int}
../target/hexagon/internal.h:28:22: note: in definition of macro
‘HEX_DEBUG_LOG’
28 | qemu_log(__VA_ARGS__); \
| ^~~~~~~~~~~
- [PATCH v7 16/35] Hexagon (target/hexagon/conv_emu.[ch]) utility functions, (continued)
- [PATCH v7 16/35] Hexagon (target/hexagon/conv_emu.[ch]) utility functions, Taylor Simpson, 2021/01/19
- [PATCH v7 04/35] Hexagon (target/hexagon) scalar core definition, Taylor Simpson, 2021/01/19
- [PATCH v7 13/35] Hexagon (target/hexagon) instruction/packet decode, Taylor Simpson, 2021/01/19
- [PATCH v7 02/35] Hexagon (target/hexagon) README, Taylor Simpson, 2021/01/19
- [PATCH v7 03/35] Hexagon (include/elf.h) ELF machine definition, Taylor Simpson, 2021/01/19
- [PATCH v7 25/35] Hexagon (target/hexagon) instruction classes, Taylor Simpson, 2021/01/19
- [PATCH v7 06/35] Hexagon (target/hexagon) register names, Taylor Simpson, 2021/01/19
- [PATCH v7 21/35] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree, Taylor Simpson, 2021/01/19
- [PATCH v7 07/35] Hexagon (target/hexagon) scalar core helpers, Taylor Simpson, 2021/01/19
- Re: [PATCH v7 07/35] Hexagon (target/hexagon) scalar core helpers,
Philippe Mathieu-Daudé <=
- [PATCH v7 10/35] Hexagon (target/hexagon) instruction and packet types, Taylor Simpson, 2021/01/19
- [PATCH v7 24/35] Hexagon (target/hexagon) macros, Taylor Simpson, 2021/01/19
- [PATCH v7 09/35] Hexagon (target/hexagon) architecture types, Taylor Simpson, 2021/01/19
- [PATCH v7 12/35] Hexagon (target/hexagon) instruction attributes, Taylor Simpson, 2021/01/19