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Re: [PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns |
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Date: |
Mon, 25 Jan 2021 15:33:02 -0800 |
On Tue, Jan 12, 2021 at 1:59 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++--
> target/riscv/vector_helper.c | 90 ++++++++++++++-----------
> 2 files changed, 74 insertions(+), 48 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 2b0e0590efc..367fb28186f 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -586,6 +586,12 @@ static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE
> * a) \
> return false; \
> }
>
> +static uint8_t vext_get_emul(DisasContext *s, uint8_t eew)
> +{
> + int8_t emul = eew - s->sew + s->lmul;
> + return emul < 0 ? 0 : emul;
> +}
> +
> /*
> *** unit stride load and store
> */
> @@ -651,8 +657,14 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a,
> uint8_t eew)
> return false;
> }
>
> + /*
> + * Vector load/store instructions have the EEW encoded
> + * directly in the instructions. The maximum vector size is
> + * calculated with EMUL rather than LMUL.
> + */
> + uint8_t emul = vext_get_emul(s, eew);
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> - data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
> }
> @@ -687,8 +699,9 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a,
> uint8_t eew)
> return false;
> }
>
> + uint8_t emul = vext_get_emul(s, eew);
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> - data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
> }
> @@ -761,8 +774,9 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a,
> uint8_t eew)
> return false;
> }
>
> + uint8_t emul = vext_get_emul(s, eew);
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> - data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
> }
> @@ -789,8 +803,9 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a,
> uint8_t eew)
> gen_helper_vsse32_v, gen_helper_vsse64_v
> };
>
> + uint8_t emul = vext_get_emul(s, eew);
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> - data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> fn = fns[eew];
> if (fn == NULL) {
> @@ -887,8 +902,9 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a,
> uint8_t eew)
>
> fn = fns[eew][s->sew];
>
> + uint8_t emul = vext_get_emul(s, s->sew);
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> - data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
> }
> @@ -938,8 +954,9 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a,
> uint8_t eew)
>
> fn = fns[eew][s->sew];
>
> + uint8_t emul = vext_get_emul(s, s->sew);
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> - data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
> }
> @@ -1003,8 +1020,9 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a,
> uint8_t eew)
> return false;
> }
>
> + uint8_t emul = vext_get_emul(s, eew);
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> - data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + data = FIELD_DP32(data, VDATA, LMUL, emul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> return ldff_trans(a->rd, a->rs1, data, fn, s);
> }
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 57564c5c0c9..8556ab3b0df 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -17,6 +17,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/host-utils.h"
> #include "cpu.h"
> #include "exec/memop.h"
> #include "exec/exec-all.h"
> @@ -121,14 +122,21 @@ static uint32_t vext_wd(uint32_t desc)
> }
>
> /*
> - * Get vector group length in bytes. Its range is [64, 2048].
> + * Get the maximum number of elements can be operated.
> *
> - * As simd_desc support at most 256, the max vlen is 512 bits.
> - * So vlen in bytes is encoded as maxsz.
> + * esz: log2 of element size in bytes.
> */
> -static inline uint32_t vext_maxsz(uint32_t desc)
> +static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
> {
> - return simd_maxsz(desc) << vext_lmul(desc);
> + /*
> + * As simd_desc support at most 256 bytes, the max vlen is 256 bits.
> + * so vlen in bytes (vlenb) is encoded as maxsz.
> + */
> + uint32_t vlenb = simd_maxsz(desc);
> +
> + /* Return VLMAX */
> + int scale = vext_lmul(desc) - esz;
> + return scale < 0 ? vlenb >> -scale : vlenb << scale;
> }
>
> /*
> @@ -221,14 +229,14 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
> {
> uint32_t i, k;
> uint32_t nf = vext_nf(desc);
> - uint32_t vlmax = vext_maxsz(desc) / esz;
> + uint32_t max_elems = vext_max_elems(desc, esz);
>
> /* probe every access*/
> for (i = 0; i < env->vl; i++) {
> if (!vm && !vext_elem_mask(v0, i)) {
> continue;
> }
> - probe_pages(env, base + stride * i, nf * esz, ra, access_type);
> + probe_pages(env, base + stride * i, nf << esz, ra, access_type);
> }
> /* do real access */
> for (i = 0; i < env->vl; i++) {
> @@ -237,8 +245,8 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
> continue;
> }
> while (k < nf) {
> - target_ulong addr = base + stride * i + k * esz;
> - ldst_elem(env, addr, i + k * vlmax, vd, ra);
> + target_ulong addr = base + stride * i + (k << esz);
> + ldst_elem(env, addr, i + k * max_elems, vd, ra);
> k++;
> }
> }
> @@ -251,7 +259,7 @@ void HELPER(NAME)(void *vd, void * v0, target_ulong base,
> \
> { \
> uint32_t vm = vext_vm(desc); \
> vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
> - sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
> + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
> }
>
> GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b)
> @@ -266,7 +274,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,
> \
> { \
> uint32_t vm = vext_vm(desc); \
> vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \
> - sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
> + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
> }
>
> GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b)
> @@ -286,16 +294,16 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState
> *env, uint32_t desc,
> {
> uint32_t i, k;
> uint32_t nf = vext_nf(desc);
> - uint32_t vlmax = vext_maxsz(desc) / esz;
> + uint32_t max_elems = vext_max_elems(desc, esz);
>
> /* probe every access */
> - probe_pages(env, base, env->vl * nf * esz, ra, access_type);
> + probe_pages(env, base, env->vl * (nf << esz), ra, access_type);
> /* load bytes from guest memory */
> for (i = 0; i < env->vl; i++) {
> k = 0;
> while (k < nf) {
> - target_ulong addr = base + (i * nf + k) * esz;
> - ldst_elem(env, addr, i + k * vlmax, vd, ra);
> + target_ulong addr = base + ((i * nf + k) << esz);
> + ldst_elem(env, addr, i + k * max_elems, vd, ra);
> k++;
> }
> }
> @@ -310,16 +318,16 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState
> *env, uint32_t desc,
> void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
> CPURISCVState *env, uint32_t desc) \
> { \
> - uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \
> + uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
> vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
> - sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
> + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
> } \
> \
> void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
> CPURISCVState *env, uint32_t desc) \
> { \
> vext_ldst_us(vd, base, env, desc, LOAD_FN, \
> - sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
> + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
> }
>
> GEN_VEXT_LD_US(vle8_v, int8_t, lde_b)
> @@ -331,16 +339,16 @@ GEN_VEXT_LD_US(vle64_v, int64_t, lde_d)
> void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
> CPURISCVState *env, uint32_t desc) \
> { \
> - uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \
> + uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
> vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
> - sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
> + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
> } \
> \
> void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
> CPURISCVState *env, uint32_t desc) \
> { \
> vext_ldst_us(vd, base, env, desc, STORE_FN, \
> - sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
> + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
> }
>
> GEN_VEXT_ST_US(vse8_v, int8_t, ste_b)
> @@ -376,14 +384,14 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
> uint32_t i, k;
> uint32_t nf = vext_nf(desc);
> uint32_t vm = vext_vm(desc);
> - uint32_t vlmax = vext_maxsz(desc) / esz;
> + uint32_t max_elems = vext_max_elems(desc, esz);
>
> /* probe every access*/
> for (i = 0; i < env->vl; i++) {
> if (!vm && !vext_elem_mask(v0, i)) {
> continue;
> }
> - probe_pages(env, get_index_addr(base, i, vs2), nf * esz, ra,
> + probe_pages(env, get_index_addr(base, i, vs2), nf << esz, ra,
> access_type);
> }
> /* load bytes from guest memory */
> @@ -393,8 +401,8 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
> continue;
> }
> while (k < nf) {
> - abi_ptr addr = get_index_addr(base, i, vs2) + k * esz;
> - ldst_elem(env, addr, i + k * vlmax, vd, ra);
> + abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz);
> + ldst_elem(env, addr, i + k * max_elems, vd, ra);
> k++;
> }
> }
> @@ -405,7 +413,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,
> \
> void *vs2, CPURISCVState *env, uint32_t desc) \
> { \
> vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
> - LOAD_FN, sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
> + LOAD_FN, ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
> }
>
> GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b)
> @@ -430,7 +438,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,
> \
> void *vs2, CPURISCVState *env, uint32_t desc) \
> { \
> vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
> - STORE_FN, sizeof(ETYPE), \
> + STORE_FN, ctzl(sizeof(ETYPE)), \
> GETPC(), MMU_DATA_STORE); \
> }
>
> @@ -464,7 +472,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
> uint32_t i, k, vl = 0;
> uint32_t nf = vext_nf(desc);
> uint32_t vm = vext_vm(desc);
> - uint32_t vlmax = vext_maxsz(desc) / esz;
> + uint32_t max_elems = vext_max_elems(desc, esz);
> target_ulong addr, offset, remain;
>
> /* probe every access*/
> @@ -472,24 +480,24 @@ vext_ldff(void *vd, void *v0, target_ulong base,
> if (!vm && !vext_elem_mask(v0, i)) {
> continue;
> }
> - addr = base + nf * i * esz;
> + addr = base + i * (nf << esz);
> if (i == 0) {
> - probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD);
> + probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
> } else {
> /* if it triggers an exception, no need to check watchpoint */
> - remain = nf * esz;
> + remain = nf << esz;
> while (remain > 0) {
> offset = -(addr | TARGET_PAGE_MASK);
> host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
> cpu_mmu_index(env, false));
> if (host) {
> #ifdef CONFIG_USER_ONLY
> - if (page_check_range(addr, nf * esz, PAGE_READ) < 0) {
> + if (page_check_range(addr, nf << esz, PAGE_READ) < 0) {
> vl = i;
> goto ProbeSuccess;
> }
> #else
> - probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD);
> + probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
> #endif
> } else {
> vl = i;
> @@ -514,8 +522,8 @@ ProbeSuccess:
> continue;
> }
> while (k < nf) {
> - target_ulong addr = base + (i * nf + k) * esz;
> - ldst_elem(env, addr, i + k * vlmax, vd, ra);
> + target_ulong addr = base + ((i * nf + k) << esz);
> + ldst_elem(env, addr, i + k * max_elems, vd, ra);
> k++;
> }
> }
> @@ -526,7 +534,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,
> \
> CPURISCVState *env, uint32_t desc) \
> { \
> vext_ldff(vd, v0, base, env, desc, LOAD_FN, \
> - sizeof(ETYPE), GETPC()); \
> + ctzl(sizeof(ETYPE)), GETPC()); \
> }
>
> GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b)
> @@ -739,7 +747,7 @@ void HELPER(NAME)(void *vs3, void *v0, target_ulong base,
> \
> { \
> vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \
> INDEX_FN, vext_##NAME##_noatomic_op, \
> - sizeof(ETYPE), GETPC()); \
> + ctzl(sizeof(ETYPE)), GETPC()); \
> }
>
> GEN_VEXT_AMO(vamoswapei8_32_v, int32_t, idx_b)
> @@ -1225,7 +1233,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
> \
> void *vs2, CPURISCVState *env, uint32_t desc) \
> { \
> uint32_t vl = env->vl; \
> - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
> + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
> uint32_t i; \
> \
> for (i = 0; i < vl; i++) { \
> @@ -3880,7 +3888,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void
> *vs2, \
> { \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
> + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
> uint32_t i; \
> \
> for (i = 0; i < vl; i++) { \
> @@ -4666,7 +4674,7 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8)
> void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
> CPURISCVState *env, uint32_t desc) \
> { \
> - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
> + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> uint32_t index, i; \
> @@ -4694,7 +4702,7 @@ GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8)
> void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> CPURISCVState *env, uint32_t desc) \
> { \
> - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
> + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> uint32_t index = s1, i; \
> --
> 2.17.1
>
>
- Re: [PATCH v6 21/72] target/riscv: rvv-1.0: fault-only-first unit stride load, (continued)
- [PATCH v6 19/72] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2021/01/12
- [PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2021/01/12
- [PATCH v6 22/72] target/riscv: rvv-1.0: amo operations, frank . chang, 2021/01/12
- [PATCH v6 23/72] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2021/01/12
- [PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2021/01/12
- Re: [PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns,
Alistair Francis <=
- [PATCH v6 25/72] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2021/01/12
- [PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2021/01/12
- [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2021/01/12
- [PATCH v6 28/72] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2021/01/12
- [PATCH v6 29/72] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/01/12
- [PATCH v6 30/72] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/01/12
- [PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/01/12