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[PULL 26/46] tests: Add a simple test of the CMSDK APB dual timer
From: |
Peter Maydell |
Subject: |
[PULL 26/46] tests: Add a simple test of the CMSDK APB dual timer |
Date: |
Fri, 29 Jan 2021 10:59:52 +0000 |
Add a simple test of the CMSDK dual timer, since we're about to do
some refactoring of how it is clocked.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210128114145.20536-6-peter.maydell@linaro.org
Message-id: 20210121190622.22000-6-peter.maydell@linaro.org
---
tests/qtest/cmsdk-apb-dualtimer-test.c | 130 +++++++++++++++++++++++++
MAINTAINERS | 1 +
tests/qtest/meson.build | 1 +
3 files changed, 132 insertions(+)
create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c
diff --git a/tests/qtest/cmsdk-apb-dualtimer-test.c
b/tests/qtest/cmsdk-apb-dualtimer-test.c
new file mode 100644
index 00000000000..ad6a758289c
--- /dev/null
+++ b/tests/qtest/cmsdk-apb-dualtimer-test.c
@@ -0,0 +1,130 @@
+/*
+ * QTest testcase for the CMSDK APB dualtimer device
+ *
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+
+/* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick */
+#define TIMER_BASE 0x40002000
+
+#define TIMER1LOAD 0
+#define TIMER1VALUE 4
+#define TIMER1CONTROL 8
+#define TIMER1INTCLR 0xc
+#define TIMER1RIS 0x10
+#define TIMER1MIS 0x14
+#define TIMER1BGLOAD 0x18
+
+#define TIMER2LOAD 0x20
+#define TIMER2VALUE 0x24
+#define TIMER2CONTROL 0x28
+#define TIMER2INTCLR 0x2c
+#define TIMER2RIS 0x30
+#define TIMER2MIS 0x34
+#define TIMER2BGLOAD 0x38
+
+#define CTRL_ENABLE (1 << 7)
+#define CTRL_PERIODIC (1 << 6)
+#define CTRL_INTEN (1 << 5)
+#define CTRL_PRESCALE_1 (0 << 2)
+#define CTRL_PRESCALE_16 (1 << 2)
+#define CTRL_PRESCALE_256 (2 << 2)
+#define CTRL_32BIT (1 << 1)
+#define CTRL_ONESHOT (1 << 0)
+
+static void test_dualtimer(void)
+{
+ g_assert_true(readl(TIMER_BASE + TIMER1RIS) == 0);
+
+ /* Start timer: will fire after 40000 ns */
+ writel(TIMER_BASE + TIMER1LOAD, 1000);
+ /* enable in free-running, wrapping, interrupt mode */
+ writel(TIMER_BASE + TIMER1CONTROL, CTRL_ENABLE | CTRL_INTEN);
+
+ /* Step to just past the 500th tick and check VALUE */
+ clock_step(500 * 40 + 1);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 500);
+
+ /* Just past the 1000th tick: timer should have fired */
+ clock_step(500 * 40);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 1);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0);
+
+ /*
+ * We are in free-running wrapping 16-bit mode, so on the following
+ * tick VALUE should have wrapped round to 0xffff.
+ */
+ clock_step(40);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0xffff);
+
+ /* Check that any write to INTCLR clears interrupt */
+ writel(TIMER_BASE + TIMER1INTCLR, 1);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0);
+
+ /* Turn off the timer */
+ writel(TIMER_BASE + TIMER1CONTROL, 0);
+}
+
+static void test_prescale(void)
+{
+ g_assert_true(readl(TIMER_BASE + TIMER2RIS) == 0);
+
+ /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */
+ writel(TIMER_BASE + TIMER2LOAD, 1000);
+ /* enable in periodic, wrapping, interrupt mode, prescale 256 */
+ writel(TIMER_BASE + TIMER2CONTROL,
+ CTRL_ENABLE | CTRL_INTEN | CTRL_PERIODIC | CTRL_PRESCALE_256);
+
+ /* Step to just past the 500th tick and check VALUE */
+ clock_step(40 * 256 * 501);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 500);
+
+ /* Just past the 1000th tick: timer should have fired */
+ clock_step(40 * 256 * 500);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 1);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 0);
+
+ /* In periodic mode the tick VALUE now reloads */
+ clock_step(40 * 256);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 1000);
+
+ /* Check that any write to INTCLR clears interrupt */
+ writel(TIMER_BASE + TIMER2INTCLR, 1);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0);
+
+ /* Turn off the timer */
+ writel(TIMER_BASE + TIMER2CONTROL, 0);
+}
+
+int main(int argc, char **argv)
+{
+ int r;
+
+ g_test_init(&argc, &argv, NULL);
+
+ qtest_start("-machine mps2-an385");
+
+ qtest_add_func("/cmsdk-apb-dualtimer/dualtimer", test_dualtimer);
+ qtest_add_func("/cmsdk-apb-dualtimer/prescale", test_prescale);
+
+ r = g_test_run();
+
+ qtest_end();
+
+ return r;
+}
diff --git a/MAINTAINERS b/MAINTAINERS
index 3729b89f359..154a91d12e5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -584,6 +584,7 @@ F: include/hw/timer/cmsdk-apb-timer.h
F: tests/qtest/cmsdk-apb-timer-test.c
F: hw/timer/cmsdk-apb-dualtimer.c
F: include/hw/timer/cmsdk-apb-dualtimer.h
+F: tests/qtest/cmsdk-apb-dualtimer-test.c
F: hw/char/cmsdk-apb-uart.c
F: include/hw/char/cmsdk-apb-uart.h
F: hw/watchdog/cmsdk-apb-watchdog.c
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 5b10bfbcfb0..c83bc211b6a 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -142,6 +142,7 @@ qtests_npcm7xx = \
'npcm7xx_timer-test',
'npcm7xx_watchdog_timer-test']
qtests_arm = \
+ (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ?
['cmsdk-apb-dualtimer-test'] : []) + \
(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ?
['cmsdk-apb-timer-test'] : []) + \
(config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ?
['cmsdk-apb-watchdog-test'] : []) + \
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] :
[]) + \
--
2.20.1
- [PULL 18/46] hw/misc/pvpanic: split-out generic and bus dependent code, (continued)
- [PULL 18/46] hw/misc/pvpanic: split-out generic and bus dependent code, Peter Maydell, 2021/01/29
- [PULL 15/46] darwin: detect CoreAudio for build, Peter Maydell, 2021/01/29
- [PULL 17/46] hvf: Add hypervisor entitlement to output binaries, Peter Maydell, 2021/01/29
- [PULL 21/46] tests/qtest: add a test case for pvpanic-pci, Peter Maydell, 2021/01/29
- [PULL 22/46] ptimer: Add new ptimer_set_period_from_clock() function, Peter Maydell, 2021/01/29
- [PULL 27/46] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer, Peter Maydell, 2021/01/29
- [PULL 29/46] hw/timer/cmsdk-apb-dualtimer: Add Clock input, Peter Maydell, 2021/01/29
- [PULL 20/46] pvpanic : update pvpanic spec document, Peter Maydell, 2021/01/29
- [PULL 24/46] tests: Add a simple test of the CMSDK APB timer, Peter Maydell, 2021/01/29
- [PULL 23/46] clock: Add new clock_has_source() function, Peter Maydell, 2021/01/29
- [PULL 26/46] tests: Add a simple test of the CMSDK APB dual timer,
Peter Maydell <=
- [PULL 25/46] tests: Add a simple test of the CMSDK APB watchdog, Peter Maydell, 2021/01/29
- [PULL 32/46] hw/arm/armsse: Wire up clocks, Peter Maydell, 2021/01/29
- [PULL 33/46] hw/arm/mps2: Inline CMSDK_APB_TIMER creation, Peter Maydell, 2021/01/29
- [PULL 34/46] hw/arm/mps2: Create and connect SYSCLK Clock, Peter Maydell, 2021/01/29
- [PULL 38/46] hw/arm/stellaris: Create Clock input for watchdog, Peter Maydell, 2021/01/29
- [PULL 36/46] hw/arm/musca: Create and connect ARMSSE Clocks, Peter Maydell, 2021/01/29
- [PULL 30/46] hw/watchdog/cmsdk-apb-watchdog: Add Clock input, Peter Maydell, 2021/01/29
- [PULL 41/46] hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input, Peter Maydell, 2021/01/29
- [PULL 40/46] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input, Peter Maydell, 2021/01/29
- [PULL 28/46] hw/timer/cmsdk-apb-timer: Add Clock input, Peter Maydell, 2021/01/29