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[RFC PATCH v3 28/31] hw/cxl/device: Plumb real LSA sizing
From: |
Ben Widawsky |
Subject: |
[RFC PATCH v3 28/31] hw/cxl/device: Plumb real LSA sizing |
Date: |
Mon, 1 Feb 2021 16:59:45 -0800 |
This should introduce no change. Subsequent work will make use of this
new class member.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
hw/cxl/cxl-mailbox-utils.c | 4 ++++
hw/mem/cxl_type3.c | 24 +++++++++---------------
include/hw/cxl/cxl.h | 1 -
include/hw/cxl/cxl_device.h | 24 ++++++++++++++++++++++++
4 files changed, 37 insertions(+), 16 deletions(-)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index dc8e0eb08e..2637250c7b 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -321,6 +321,9 @@ define_mailbox_handler(IDENTIFY_MEMORY_DEVICE)
} __attribute__((packed)) *id;
_Static_assert(sizeof(*id) == 0x43, "Bad identify size");
+ CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
+ CXLType3Class *cvc = CXL_TYPE3_DEV_GET_CLASS(ct3d);
+
if (memory_region_size(cxl_dstate->pmem) < (256 << 20)) {
return CXL_MBOX_INTERNAL_ERROR;
}
@@ -332,6 +335,7 @@ define_mailbox_handler(IDENTIFY_MEMORY_DEVICE)
snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0);
id->total_capacity = memory_region_size(cxl_dstate->pmem);
id->persistent_capacity = memory_region_size(cxl_dstate->pmem);
+ id->lsa_size = cvc->get_lsa_size(ct3d);
*len = sizeof(*id);
return CXL_MBOX_SUCCESS;
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index fe02c3b63c..074d1dd41f 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -13,21 +13,6 @@
#include "sysemu/hostmem.h"
#include "hw/cxl/cxl.h"
-typedef struct cxl_type3_dev {
- /* Private */
- PCIDevice parent_obj;
-
- /* Properties */
- uint64_t size;
- HostMemoryBackend *hostmem;
-
- /* State */
- CXLComponentState cxl_cstate;
- CXLDeviceState cxl_dstate;
-} CXLType3Dev;
-
-#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV)
-
static void build_dvsecs(CXLType3Dev *ct3d)
{
CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
@@ -310,11 +295,17 @@ static void pc_dimm_md_fill_device_info(const
MemoryDeviceState *md,
info->type = MEMORY_DEVICE_INFO_KIND_CXL;
}
+static uint64_t get_lsa_size(CXLType3Dev *ct3d)
+{
+ return 0;
+}
+
static void ct3_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
MemoryDeviceClass *mdc = MEMORY_DEVICE_CLASS(oc);
+ CXLType3Class *cvc = CXL_TYPE3_DEV_CLASS(oc);
pc->realize = ct3_realize;
pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
@@ -332,11 +323,14 @@ static void ct3_class_init(ObjectClass *oc, void *data)
mdc->fill_device_info = pc_dimm_md_fill_device_info;
mdc->get_plugged_size = memory_device_get_region_size;
mdc->set_addr = cxl_md_set_addr;
+
+ cvc->get_lsa_size = get_lsa_size;
}
static const TypeInfo ct3d_info = {
.name = TYPE_CXL_TYPE3_DEV,
.parent = TYPE_PCI_DEVICE,
+ .class_size = sizeof(struct CXLType3Class),
.class_init = ct3_class_init,
.instance_size = sizeof(CXLType3Dev),
.instance_init = ct3_instance_init,
diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
index 809ed7de60..c7ca42930f 100644
--- a/include/hw/cxl/cxl.h
+++ b/include/hw/cxl/cxl.h
@@ -23,4 +23,3 @@
#define CXL_WINDOW_MAX 10
#endif
-
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index ca5328a581..a79a0f106c 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -219,4 +219,28 @@ REG32(CXL_MEM_DEV_STS, 0)
FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
+typedef struct cxl_type3_dev {
+ /* Private */
+ PCIDevice parent_obj;
+
+ /* Properties */
+ uint64_t size;
+ HostMemoryBackend *hostmem;
+ HostMemoryBackend *lsa;
+
+ /* State */
+ CXLComponentState cxl_cstate;
+ CXLDeviceState cxl_dstate;
+} CXLType3Dev;
+
+#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV)
+
+struct CXLType3Class {
+ /* Private */
+ PCIDeviceClass parent_class;
+
+ /* public */
+ uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
+};
+
#endif
--
2.30.0
- [RFC PATCH v3 20/31] hw/cxl/rp: Add a root port, (continued)
- [RFC PATCH v3 20/31] hw/cxl/rp: Add a root port, Ben Widawsky, 2021/02/01
- [RFC PATCH v3 21/31] hw/cxl/device: Add a memory device (8.2.8.5), Ben Widawsky, 2021/02/01
- [RFC PATCH v3 22/31] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12), Ben Widawsky, 2021/02/01
- [RFC PATCH v3 23/31] acpi/cxl: Add _OSC implementation (9.14.2), Ben Widawsky, 2021/02/01
- [RFC PATCH v3 24/31] tests/acpi: allow CEDT table addition, Ben Widawsky, 2021/02/01
- [RFC PATCH v3 25/31] acpi/cxl: Create the CEDT (9.14.1), Ben Widawsky, 2021/02/01
- [RFC PATCH v3 26/31] tests/acpi: Add new CEDT files, Ben Widawsky, 2021/02/01
- [RFC PATCH v3 27/31] hw/cxl/device: Add some trivial commands, Ben Widawsky, 2021/02/01
- [RFC PATCH v3 28/31] hw/cxl/device: Plumb real LSA sizing,
Ben Widawsky <=
- [RFC PATCH v3 29/31] hw/cxl/device: Implement get/set LSA, Ben Widawsky, 2021/02/01
- [RFC PATCH v3 31/31] WIP: i386/cxl: Initialize a host bridge, Ben Widawsky, 2021/02/01
- [RFC PATCH v3 30/31] qtest/cxl: Add very basic sanity tests, Ben Widawsky, 2021/02/01
- Re: [RFC PATCH v3 00/31] CXL 2.0 Support, no-reply, 2021/02/01
- Re: [RFC PATCH v3 00/31] CXL 2.0 Support, Ben Widawsky, 2021/02/03