[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 00/21] target-arm queue
From: |
Peter Maydell |
Subject: |
[PULL v2 00/21] target-arm queue |
Date: |
Wed, 3 Feb 2021 10:17:15 +0000 |
no changes to v1, except adding the CVE identifier to one of the commit
messages.
-- PMM
The following changes since commit cf7ca7d5b9faca13f1f8e3ea92cfb2f741eb0c0e:
Merge remote-tracking branch
'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2021-02-01
16:28:00 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210203
for you to fetch changes up to fd8f71b95da86f530aae3d02a14b0ccd9e024772:
hw/arm: Display CPU type in machine description (2021-02-03 10:15:51 +0000)
----------------------------------------------------------------
target-arm queue:
* hw/intc/arm_gic: Allow to use QTest without crashing
* hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
* hw/char/exynos4210_uart: Fix missing call to report ready for input
* hw/arm/smmuv3: Fix addr_mask for range-based invalidation
* hw/ssi/imx_spi: Fix various minor bugs
* hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
* hw/arm: Add missing Kconfig dependencies
* hw/arm: Display CPU type in machine description
----------------------------------------------------------------
Bin Meng (5):
hw/ssi: imx_spi: Use a macro for number of chip selects supported
hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()
hw/ssi: imx_spi: Round up the burst length to be multiple of 8
hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic
hw/ssi: imx_spi: Correct tx and rx fifo endianness
Iris Johnson (2):
hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
hw/char/exynos4210_uart: Fix missing call to report ready for input
Philippe Mathieu-Daudé (12):
hw/intc/arm_gic: Allow to use QTest without crashing
hw/ssi: imx_spi: Remove pointless variable initialization
hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ
hw/arm/exynos4210: Add missing dependency on OR_IRQ
hw/arm/xlnx-versal: Versal SoC requires ZDMA
hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals
hw/net/can: ZynqMP CAN device requires PTIMER
hw/arm: Display CPU type in machine description
Xuzhou Cheng (1):
hw/ssi: imx_spi: Disable chip selects when controller is disabled
Zenghui Yu (1):
hw/arm/smmuv3: Fix addr_mask for range-based invalidation
include/hw/ssi/imx_spi.h | 5 +-
hw/arm/digic_boards.c | 2 +-
hw/arm/microbit.c | 2 +-
hw/arm/netduino2.c | 2 +-
hw/arm/netduinoplus2.c | 2 +-
hw/arm/orangepi.c | 2 +-
hw/arm/smmuv3.c | 4 +-
hw/arm/stellaris.c | 4 +-
hw/char/exynos4210_uart.c | 7 ++-
hw/intc/arm_gic.c | 5 +-
hw/ssi/imx_spi.c | 153 +++++++++++++++++++++++++++++-----------------
hw/Kconfig | 1 +
hw/arm/Kconfig | 5 ++
hw/dma/Kconfig | 3 +
hw/dma/meson.build | 2 +-
15 files changed, 130 insertions(+), 69 deletions(-)
- [PULL v2 00/21] target-arm queue,
Peter Maydell <=