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[PATCH v2 6/9] hw/i386: declare ACPI mother board resource for MMCONFIG
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From: |
isaku . yamahata |
|
Subject: |
[PATCH v2 6/9] hw/i386: declare ACPI mother board resource for MMCONFIG region |
|
Date: |
Mon, 8 Feb 2021 13:57:25 -0800 |
From: Isaku Yamahata <isaku.yamahata@intel.com>
Declare PNP0C01 device to reserve MMCONFIG region to conform to the
spec better and play nice with guest BIOSes/OSes.
According to PCI Firmware Specification, MMCONFIG region must be
reserved by declaring a motherboard resource. It's optional to reserve
the region in memory map by Int 15 E820h or EFIGetMemoryMap.
If guest BIOS doesn't reserve the region in memory map without the
reservation by mother board resource, guest linux abandons to use
MMCFG.
TDVF [0] [1] doesn't reserve MMCONFIG the region in memory map.
On the other hand OVMF reserves it in memory map without declaring a
motherboard resource. With memory map reservation, linux guest uses
MMCONFIG region. However it doesn't comply to PCI Firmware
specification.
[0] TDX: Intel Trust Domain Extension
https://software.intel.com/content/www/us/en/develop/articles/intel-trust-domain-extensions.html
[1] TDX Virtual Firmware
https://github.com/tianocore/edk2-staging/tree/TDVF
The change to DSDT is as follows.
@@ -68,32 +68,90 @@
If ((CDW3 != Local0))
{
CDW1 |= 0x10
}
CDW3 = Local0
}
Else
{
CDW1 |= 0x04
}
Return (Arg3)
}
}
+
+ Device (DRAC)
+ {
+ Name (_HID, "PNP0C01" /* System Board */) // _HID: Hardware ID
+ OperationRegion (DRR0, PCI_Config, 0x60, 0x08)
+ Field (DRR0, DWordAcc, NoLock, Preserve)
+ {
+ PEBL, 32,
+ PEBH, 32
+ }
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Range Minimum
+ 0x0000000000000000, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000000000000, // Length
+ ,, _Y00, AddressRangeMemory, TypeStatic)
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ CreateDWordField (RBUF, \_SB.DRAC._Y00._MIN, MINL) // _MIN:
Minimum Base Address
+ CreateDWordField (RBUF, 0x12, MINH)
+ CreateDWordField (RBUF, \_SB.DRAC._Y00._MAX, MAXL) // _MAX:
Maximum Base Address
+ CreateDWordField (RBUF, 0x1A, MAXH)
+ CreateQWordField (RBUF, \_SB.DRAC._Y00._LEN, _LEN) // _LEN:
Length
+ Local0 = PEBL /* \_SB_.DRAC.PEBL */
+ Local1 = (Local0 & One)
+ Local2 = (Local0 & 0x06)
+ Local3 = (Local0 & 0xFFFFFFF8)
+ Local4 = PEBH /* \_SB_.DRAC.PEBH */
+ If ((Local1 == One))
+ {
+ MINL = Local3
+ MINH = Local4
+ MAXL = Local3
+ MAXH = Local4
+ If ((Local2 == Zero))
+ {
+ _LEN = 0x10000000
+ }
+
+ If ((Local2 == 0x02))
+ {
+ _LEN = 0x08000000
+ }
+
+ If ((Local2 == 0x04))
+ {
+ _LEN = 0x04000000
+ }
+ }
+
+ Return (RBUF) /* \_SB_.DRAC.RBUF */
+ }
+ }
}
Scope (_SB)
{
Device (HPET)
{
Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID:
Hardware ID
Name (_UID, Zero) // _UID: Unique ID
OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
Field (HPTM, DWordAcc, Lock, Preserve)
{
VEND, 32,
PRD, 32
}
Method (_STA, 0, NotSerialized) // _STA: Status
Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
---
hw/i386/acpi-build.c | 172 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 172 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index c2f11d95d8..bcb1f65c1d 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1066,6 +1066,177 @@ static void build_q35_pci0_int(Aml *table)
aml_append(table, sb_scope);
}
+static Aml *build_q35_dram_controller(void)
+{
+ /*
+ * DSDT is created with revision 1 which means 32bit integer.
+ * When the method of _CRS is called to determine MMCONFIG region,
+ * only port io is allowed to access PCI configuration space.
+ * It means qword access isn't allowed.
+ *
+ * Device(DRAC)
+ * {
+ * Name(_HID, EisaId("PNP0C01"))
+ * OperationRegion(DRR0, PCI_Config, 0x0000000000000060, 0x8)
+ * Field(DRR0, DWordAcc, Lock, Preserve)
+ * {
+ * PEBL, 4,
+ * PEBH, 4
+ * }
+ * Name(RBUF, ResourceTemplate()
+ * {
+ * QWordMemory(ResourceConsumer,
+ * PosDecode,
+ * MinFixed,
+ * MaxFixed,
+ * NonCacheable,
+ * ReadWrite,
+ * 0x0000000000000000, // Granularity
+ * 0x0000000000000000, // Range Minimum
+ * 0x0000000000000000, // Range Maxium
+ * 0x0000000000000000, // Translation Offset,
+ * 0x0000000000000000, // Length,
+ * ,,
+ * _MCF,
+ * AddressRangeMemory,
+ * TypeStatic
+ * )
+ * })
+ * Method(_CRS, 0x0, NotSerialized)
+ * {
+ * CreateDWordField(RBUF, DRAC._MCF._MIN, MINL)
+ * CreateDWordField(RBUF, DRAC._MCF._MIN + 4, MINH)
+ * CreateDWordField(RBUF, DRAC._MCF._MAX, MAXL)
+ * CreateDWordField(RBUF, DRAC._MCF._MAX + 4, MAXH)
+ * CreateQWordField(RBUF, DRAC._MCF._LEN, _LEN)
+ *
+ * Local0 = PEBL
+ * Local1 = Local0 & 0x1 // PCIEXBAR PCIEBAREN
+ * Local2 = Local0 & 0x6 // PCIEXBAR LENGTH
+ * Local3 = Local0 & ~0x7 // PCIEXBAR base address low 32bit
+ * Local4 = PEBH // PCIEXBAR base address high 32bit
+ * If (Local1 == 1) {
+ * MINL = Local3
+ * MINH = Local4
+ * MAXL = Local3
+ * MAXH = Local4
+ *
+ * If (Local2 == 0) {
+ * _LEN = 256 * 1024 * 1024
+ * }
+ * If (Local2 == 0x2) {
+ * _LEN = 128 * 1024 * 1024
+ * }
+ * If (Local2 == 0x4) {
+ * _LEN = 64 * 1024 * 1024
+ * }
+ * }
+ * return (RBUF)
+ * }
+ * }
+ */
+
+ Aml *dev;
+ Aml *field;
+ Aml *rbuf;
+ Aml *resource_template;
+ Aml *crs;
+
+ /* DRAM controller */
+ dev = aml_device("DRAC");
+
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
+ /* 5.1.6 PCIEXBAR: Bus 0:Device 0:Function 0:offset 0x60 */
+ aml_append(dev, aml_operation_region("DRR0", AML_PCI_CONFIG,
+ aml_int(0x0000000000000060), 0x8));
+ field = aml_field("DRR0", AML_DWORD_ACC, AML_NOLOCK, AML_PRESERVE);
+ aml_append(field, aml_named_field("PEBL", 32));
+ aml_append(field, aml_named_field("PEBH", 32));
+ aml_append(dev, field);
+
+ resource_template = aml_resource_template();
+ aml_append(resource_template, aml_qword_memory(AML_POS_DECODE,
+ AML_MIN_FIXED,
+ AML_MAX_FIXED,
+ AML_NON_CACHEABLE,
+ AML_READ_WRITE,
+ 0x0000000000000000,
+ 0x0000000000000000,
+ 0x0000000000000000,
+ 0x0000000000000000,
+ 0x0000000000000000));
+ rbuf = aml_name_decl("RBUF", resource_template);
+ aml_append(dev, rbuf);
+
+ crs = aml_method("_CRS", 0, AML_SERIALIZED);
+ {
+ Aml *rbuf_name;
+ Aml *local0;
+ Aml *local1;
+ Aml *local2;
+ Aml *local3;
+ Aml *local4;
+ Aml *ifc;
+
+ rbuf_name = aml_name("RBUF");
+ aml_append(crs, aml_create_dword_field(rbuf_name,
+ aml_int(14), "MINL"));
+ aml_append(crs, aml_create_dword_field(rbuf_name,
+ aml_int(14 + 4), "MINH"));
+ aml_append(crs, aml_create_dword_field(rbuf_name,
+ aml_int(22), "MAXL"));
+ aml_append(crs, aml_create_dword_field(rbuf_name,
+ aml_int(22 + 4), "MAXH"));
+ aml_append(crs, aml_create_qword_field(rbuf_name,
+ aml_int(38), "_LEN"));
+
+ local0 = aml_local(0);
+ aml_append(crs, aml_store(aml_name("PEBL"), local0));
+ local1 = aml_local(1);
+ aml_append(crs, aml_and(local0, aml_int(0x1), local1));
+ local2 = aml_local(2);
+ aml_append(crs, aml_and(local0, aml_int(0x6), local2));
+ local3 = aml_local(3);
+ aml_append(crs, aml_and(local0, aml_int((uint32_t)~0x7), local3));
+ local4 = aml_local(4);
+ aml_append(crs, aml_store(aml_name("PEBH"), local4));
+
+ ifc = aml_if(aml_equal(local1, aml_int(0x1)));
+ {
+ Aml *_len;
+ Aml *ifc0;
+ Aml *ifc2;
+ Aml *ifc4;
+
+ aml_append(ifc, aml_store(local3, aml_name("MINL")));
+ aml_append(ifc, aml_store(local4, aml_name("MINH")));
+ aml_append(ifc, aml_store(local3, aml_name("MAXL")));
+ aml_append(ifc, aml_store(local4, aml_name("MAXH")));
+
+ _len = aml_name("_LEN");
+ ifc0 = aml_if(aml_equal(local2, aml_int(0x0)));
+ aml_append(ifc0,
+ aml_store(aml_int(256 * 1024 * 1024), _len));
+ aml_append(ifc, ifc0);
+
+ ifc2 = aml_if(aml_equal(local2, aml_int(0x2)));
+ aml_append(ifc2,
+ aml_store(aml_int(128 * 1024 * 1024), _len));
+ aml_append(ifc, ifc2);
+
+ ifc4 = aml_if(aml_equal(local2, aml_int(0x4)));
+ aml_append(ifc4,
+ aml_store(aml_int(64 * 1024 * 1024), _len));
+ aml_append(ifc, ifc4);
+ }
+ aml_append(crs, ifc);
+ aml_append(crs, aml_return(rbuf_name));
+ }
+ aml_append(dev, crs);
+
+ return dev;
+}
+
static void build_q35_isa_bridge(Aml *table)
{
Aml *dev;
@@ -1250,6 +1421,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
aml_append(dev, aml_name_decl("_UID", aml_int(0)));
aml_append(dev, build_q35_osc_method());
aml_append(sb_scope, dev);
+ aml_append(sb_scope, build_q35_dram_controller());
if (pm->smi_on_cpuhp) {
/* reserve SMI block resources, IO ports 0xB2, 0xB3 */
--
2.17.1
- [PATCH v2 0/9] ACPI related fixes, isaku . yamahata, 2021/02/08
- [PATCH v2 1/9] checkpatch: don't emit warning on newly created acpi data files, isaku . yamahata, 2021/02/08
- [PATCH v2 2/9] qtest: update tests/qtest/bios-tables-test-allowed-diff.h, isaku . yamahata, 2021/02/08
- [PATCH v2 4/9] acpi: set fadt.smi_cmd to zero when SMM is not supported, isaku . yamahata, 2021/02/08
- [PATCH v2 6/9] hw/i386: declare ACPI mother board resource for MMCONFIG region,
isaku . yamahata <=
- Re: [PATCH v2 6/9] hw/i386: declare ACPI mother board resource for MMCONFIG region, Michael S. Tsirkin, 2021/02/10
[PATCH v2 5/9] acpi: add test case for smm unsupported -machine smm=off, isaku . yamahata, 2021/02/08
[PATCH v2 9/9] qtest/acpi/bios-tables-test: update acpi tables, isaku . yamahata, 2021/02/08