[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 18/21] accel/tcg: re-factor non-RAM execution code
From: |
Alex Bennée |
Subject: |
[PATCH v2 18/21] accel/tcg: re-factor non-RAM execution code |
Date: |
Wed, 10 Feb 2021 22:10:50 +0000 |
There is no real need to use CF_NOCACHE here. As long as the TB isn't
linked to other TBs or included in the QHT or jump cache then it will
only get executed once.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210209182749.31323-10-alex.bennee@linaro.org>
---
accel/tcg/translate-all.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index b8ad95aa1b..7e62d8ad97 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1778,7 +1778,8 @@ static inline void tb_page_add(PageDesc *p,
TranslationBlock *tb,
#endif
}
-/* add a new TB and link it to the physical page tables. phys_page2 is
+/*
+ * Add a new TB and link it to the physical page tables. phys_page2 is
* (-1) to indicate that only one page contains the TB.
*
* Called with mmap_lock held for user-mode emulation.
@@ -1797,17 +1798,6 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t
phys_pc,
assert_memory_lock();
- if (phys_pc == -1) {
- /*
- * If the TB is not associated with a physical RAM page then
- * it must be a temporary one-insn TB, and we have nothing to do
- * except fill in the page_addr[] fields.
- */
- assert(tb->cflags & CF_NOCACHE);
- tb->page_addr[0] = tb->page_addr[1] = -1;
- return tb;
- }
-
/*
* Add the TB to the page list, acquiring first the pages's locks.
* We keep the locks held until after inserting the TB in the hash table,
@@ -1880,9 +1870,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
phys_pc = get_page_addr_code(env, pc);
if (phys_pc == -1) {
- /* Generate a temporary TB with 1 insn in it */
- cflags &= ~CF_COUNT_MASK;
- cflags |= CF_NOCACHE | 1;
+ /* Generate a one-shot TB with 1 insn in it */
+ cflags = (cflags & ~CF_COUNT_MASK) | 1;
}
cflags &= ~CF_CLUSTER_MASK;
@@ -2096,6 +2085,17 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tb_reset_jump(tb, 1);
}
+ /*
+ * If the TB is not associated with a physical RAM page then
+ * it must be a temporary one-insn TB, and we have nothing to do
+ * except fill in the page_addr[] fields. Return early before
+ * attempting to link to other TBs or add to the lookup table.
+ */
+ if (phys_pc == -1) {
+ tb->page_addr[0] = tb->page_addr[1] = -1;
+ return tb;
+ }
+
/* check next page if needed */
virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
phys_page2 = -1;
--
2.20.1
- [PATCH v2 11/21] accel/tcg: Create io_recompile_replay_branch hook, (continued)
- [PATCH v2 11/21] accel/tcg: Create io_recompile_replay_branch hook, Alex Bennée, 2021/02/10
- [PATCH v2 13/21] target/sh4: Create superh_io_recompile_replay_branch, Alex Bennée, 2021/02/10
- [PATCH v2 10/21] exec: Move TranslationBlock typedef to qemu/typedefs.h, Alex Bennée, 2021/02/10
- [PATCH v2 21/21] tests/acceptance: add a new tests to detect counting errors, Alex Bennée, 2021/02/10
- [PATCH v2 18/21] accel/tcg: re-factor non-RAM execution code,
Alex Bennée <=
- [PATCH v2 19/21] accel/tcg: remove CF_NOCACHE and special cases, Alex Bennée, 2021/02/10
- [PATCH v2 17/21] accel/tcg: cache single instruction TB on pending replay exception, Alex Bennée, 2021/02/10
- [PATCH v2 15/21] tests/acceptance: add a new set of tests to exercise plugins, Alex Bennée, 2021/02/10
- [PATCH v2 16/21] accel/tcg: actually cache our partial icount TB, Alex Bennée, 2021/02/10