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[PULL 00/45] target-arm queue
From: |
Peter Maydell |
Subject: |
[PULL 00/45] target-arm queue |
Date: |
Thu, 11 Feb 2021 12:58:15 +0000 |
Arm queue; the big bit here is RTH's MTE for user-mode series.
-- PMM
The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
Merge remote-tracking branch
'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10
15:42:20 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210211
for you to fetch changes up to 5213c78932ecf4bae18d62baf8735724e25fb478:
target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 11:50:16 +0000)
----------------------------------------------------------------
target-arm queue:
* Correctly initialize MDCR_EL2.HPMN
* versal: Use nr_apu_cpus in favor of hard coding 2
* npcm7xx: Add ethernet device
* Enable ARMv8.4-MemTag for user-mode emulation
* accel/tcg: Add URL of clang bug to comment about our workaround
* Add support for FEAT_DIT, Data Independent Timing
* Remove GPIO from unimplemented NPCM7XX
* Fix SCR RES1 handling
* Don't migrate CPUARMState.features
----------------------------------------------------------------
Aaron Lindsay (1):
target/arm: Don't migrate CPUARMState.features
Daniel Müller (1):
target/arm: Correctly initialize MDCR_EL2.HPMN
Doug Evans (3):
hw/net: Add npcm7xx emc model
hw/arm: Add npcm7xx emc model
tests/qtests: Add npcm7xx emc model test
Edgar E. Iglesias (1):
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
Hao Wu (1):
hw/arm: Remove GPIO from unimplemented NPCM7XX
Mike Nawrocki (1):
target/arm: Fix SCR RES1 handling
Peter Maydell (2):
arm: Update infocenter.arm.com URLs
accel/tcg: Add URL of clang bug to comment about our workaround
Rebecca Cran (4):
target/arm: Add support for FEAT_DIT, Data Independent Timing
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into
env->pstate
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
Richard Henderson (31):
tcg: Introduce target-specific page data for user-only
linux-user: Introduce PAGE_ANON
exec: Use uintptr_t for guest_base
exec: Use uintptr_t in cpu_ldst.h
exec: Improve types for guest_addr_valid
linux-user: Check for overflow in access_ok
linux-user: Tidy VERIFY_READ/VERIFY_WRITE
bsd-user: Tidy VERIFY_READ/VERIFY_WRITE
linux-user: Do not use guest_addr_valid for h2g_valid
linux-user: Fix guest_addr_valid vs reserved_va
exec: Introduce cpu_untagged_addr
exec: Use cpu_untagged_addr in g2h; split out g2h_untagged
linux-user: Explicitly untag memory management syscalls
linux-user: Use guest_range_valid in access_ok
exec: Rename guest_{addr,range}_valid to *_untagged
linux-user: Use cpu_untagged_addr in access_ok; split out *_untagged
linux-user: Move lock_user et al out of line
linux-user: Fix types in uaccess.c
linux-user: Handle tags in lock_user/unlock_user
linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE
target/arm: Improve gen_top_byte_ignore
target/arm: Use the proper TBI settings for linux-user
linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG
linux-user/aarch64: Implement PROT_MTE
target/arm: Split out syndrome.h from internals.h
linux-user/aarch64: Pass syndrome to EXC_*_ABORT
linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault
linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error
target/arm: Add allocation tag storage for user mode
target/arm: Enable MTE for user-only
tests/tcg/aarch64: Add mte smoke tests
docs/system/arm/nuvoton.rst | 3 +-
bsd-user/qemu.h | 9 +-
include/exec/cpu-all.h | 47 +-
include/exec/cpu_ldst.h | 39 +-
include/exec/exec-all.h | 2 +-
include/hw/arm/npcm7xx.h | 2 +
include/hw/dma/pl080.h | 7 +-
include/hw/misc/arm_integrator_debug.h | 2 +-
include/hw/net/npcm7xx_emc.h | 286 +++++++++++
include/hw/ssi/pl022.h | 5 +-
linux-user/aarch64/target_signal.h | 3 +
linux-user/aarch64/target_syscall.h | 13 +
linux-user/qemu.h | 76 +--
linux-user/syscall_defs.h | 1 +
target/arm/cpu-param.h | 3 +
target/arm/cpu.h | 49 ++
target/arm/internals.h | 255 +---------
target/arm/syndrome.h | 273 +++++++++++
tests/tcg/aarch64/mte.h | 60 +++
accel/tcg/cpu-exec.c | 25 +-
accel/tcg/translate-all.c | 32 +-
accel/tcg/user-exec.c | 51 +-
bsd-user/main.c | 4 +-
hw/arm/aspeed_ast2600.c | 2 +-
hw/arm/musca.c | 4 +-
hw/arm/npcm7xx.c | 58 ++-
hw/arm/xlnx-versal.c | 4 +-
hw/misc/arm_integrator_debug.c | 2 +-
hw/net/npcm7xx_emc.c | 857 +++++++++++++++++++++++++++++++++
hw/timer/arm_timer.c | 7 +-
linux-user/aarch64/cpu_loop.c | 38 +-
linux-user/elfload.c | 18 +-
linux-user/flatload.c | 2 +-
linux-user/hppa/cpu_loop.c | 39 +-
linux-user/i386/cpu_loop.c | 6 +-
linux-user/i386/signal.c | 5 +-
linux-user/main.c | 4 +-
linux-user/mmap.c | 86 ++--
linux-user/ppc/signal.c | 4 +-
linux-user/syscall.c | 165 +++++--
linux-user/uaccess.c | 82 +++-
target/arm/cpu.c | 29 +-
target/arm/cpu64.c | 5 +
target/arm/helper-a64.c | 31 +-
target/arm/helper.c | 71 ++-
target/arm/machine.c | 2 +-
target/arm/mte_helper.c | 39 +-
target/arm/op_helper.c | 9 +-
target/arm/tlb_helper.c | 15 +-
target/arm/translate-a64.c | 37 +-
target/hppa/op_helper.c | 2 +-
target/i386/tcg/mem_helper.c | 2 +-
target/s390x/mem_helper.c | 4 +-
tests/qtest/npcm7xx_emc-test.c | 812 +++++++++++++++++++++++++++++++
tests/tcg/aarch64/mte-1.c | 28 ++
tests/tcg/aarch64/mte-2.c | 45 ++
tests/tcg/aarch64/mte-3.c | 51 ++
tests/tcg/aarch64/mte-4.c | 45 ++
tests/tcg/aarch64/pauth-2.c | 1 -
hw/net/meson.build | 1 +
hw/net/trace-events | 17 +
tests/qtest/meson.build | 1 +
tests/tcg/aarch64/Makefile.target | 6 +
tests/tcg/configure.sh | 4 +
64 files changed, 3312 insertions(+), 575 deletions(-)
create mode 100644 include/hw/net/npcm7xx_emc.h
create mode 100644 target/arm/syndrome.h
create mode 100644 tests/tcg/aarch64/mte.h
create mode 100644 hw/net/npcm7xx_emc.c
create mode 100644 tests/qtest/npcm7xx_emc-test.c
create mode 100644 tests/tcg/aarch64/mte-1.c
create mode 100644 tests/tcg/aarch64/mte-2.c
create mode 100644 tests/tcg/aarch64/mte-3.c
create mode 100644 tests/tcg/aarch64/mte-4.c
- [PULL 00/45] target-arm queue,
Peter Maydell <=
- [PULL 01/45] target/arm: Don't migrate CPUARMState.features, Peter Maydell, 2021/02/11
- [PULL 05/45] target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate, Peter Maydell, 2021/02/11
- [PULL 07/45] target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU, Peter Maydell, 2021/02/11
- [PULL 04/45] target/arm: Add support for FEAT_DIT, Data Independent Timing, Peter Maydell, 2021/02/11
- [PULL 02/45] target/arm: Fix SCR RES1 handling, Peter Maydell, 2021/02/11
- [PULL 08/45] arm: Update infocenter.arm.com URLs, Peter Maydell, 2021/02/11
- [PULL 03/45] hw/arm: Remove GPIO from unimplemented NPCM7XX, Peter Maydell, 2021/02/11
- [PULL 06/45] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU, Peter Maydell, 2021/02/11
- [PULL 09/45] accel/tcg: Add URL of clang bug to comment about our workaround, Peter Maydell, 2021/02/11
- [PULL 10/45] tcg: Introduce target-specific page data for user-only, Peter Maydell, 2021/02/11