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[PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field
From: |
frank . chang |
Subject: |
[PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field |
Date: |
Fri, 26 Feb 2021 11:17:47 +0800 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 7 +++++++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 15 ++++++++++++++-
target/riscv/csr.c | 25 ++++++++++++++++++++++++-
4 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9d911f81093..2c1e6c46a2d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -327,6 +327,7 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray
*buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
+bool riscv_cpu_vector_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
@@ -373,6 +374,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_PRIV_MMU_MASK 3
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
+#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
typedef CPURISCVState CPUArchState;
typedef RISCVCPU ArchCPU;
@@ -428,6 +430,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env,
target_ulong *pc,
#ifdef CONFIG_USER_ONLY
flags |= TB_FLAGS_MSTATUS_FS;
+ flags |= TB_FLAGS_MSTATUS_VS;
#else
flags |= cpu_mmu_index(env, 0);
if (riscv_cpu_fp_enabled(env)) {
@@ -442,6 +445,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState
*env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
}
+
+ if (riscv_cpu_vector_enabled(env)) {
+ flags |= env->mstatus & MSTATUS_VS;
+ }
#endif
*pflags = flags;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 4196ef8b692..ba4c1c7076f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -370,6 +370,7 @@
#define MSTATUS_SPIE 0x00000020
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100
+#define MSTATUS_VS 0x00000600
#define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000
#define MSTATUS_XS 0x00018000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 2f43939fb6d..b07e10d472f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -109,11 +109,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
return false;
}
+/* Return true is vector support is currently enabled */
+bool riscv_cpu_vector_enabled(CPURISCVState *env)
+{
+ if (env->mstatus & MSTATUS_VS) {
+ if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) {
+ return false;
+ }
+ return true;
+ }
+
+ return false;
+}
+
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
- MSTATUS64_UXL;
+ MSTATUS64_UXL | MSTATUS_VS;
bool current_virt = riscv_cpu_virt_enabled(env);
g_assert(riscv_has_ext(env, RVH));
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d2ae73e4a08..778d5b85e92 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -260,6 +260,7 @@ static int write_fcsr(CPURISCVState *env, int csrno,
target_ulong val)
return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_VS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
if (vs(env, csrno) >= 0) {
@@ -290,6 +291,13 @@ static int read_vxrm(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
env->vxrm = val;
return 0;
}
@@ -302,6 +310,13 @@ static int read_vxsat(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
env->vxsat = val;
return 0;
}
@@ -314,6 +329,13 @@ static int read_vstart(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
env->vstart = val;
return 0;
}
@@ -477,7 +499,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
- MSTATUS_TW;
+ MSTATUS_TW | MSTATUS_VS;
if (!riscv_cpu_is_32bit(env)) {
/*
@@ -490,6 +512,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
mstatus = (mstatus & ~mask) | (val & mask);
dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
+ ((mstatus & MSTATUS_VS) == MSTATUS_VS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
mstatus = set_field(mstatus, MSTATUS_SD, dirty);
env->mstatus = mstatus;
--
2.17.1
- [PATCH v7 00/75] support vector extension v1.0, frank . chang, 2021/02/25
- [PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/02/25
- [PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/02/25
- [PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field,
frank . chang <=
- [PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/02/25
- [PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/02/25
- [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/02/25
- [PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/02/25
- [PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/02/25
- [PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/02/25
- [PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/02/25
- [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/02/25
- [PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/02/25
- [PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/02/25