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[PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs
From: |
frank . chang |
Subject: |
[PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs |
Date: |
Fri, 26 Feb 2021 11:18:55 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/csr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e0f1106d909..0082db9cc0c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -209,7 +209,7 @@ static int write_fflags(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_FS | MSTATUS_SD;
#endif
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
return 0;
@@ -232,7 +232,7 @@ static int write_frm(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_FS | MSTATUS_SD;
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
return 0;
@@ -256,7 +256,7 @@ static int write_fcsr(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_FS | MSTATUS_SD;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
--
2.17.1
- [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, (continued)
- [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/02/25
- [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/02/25
- [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/02/25
- [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/02/25
- [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/02/25
- [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/02/25
- [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/02/25
- [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs, frank . chang, 2021/02/25
- [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/02/25
- [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/02/25
- [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs,
frank . chang <=
- [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/02/25
- [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/02/25
- [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/02/25
- [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/02/25
- [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 2021/02/25