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[RFC v13 63/80] target/arm: make is_aa64 and arm_el_is_aa64 a macro for
From: |
Claudio Fontana |
Subject: |
[RFC v13 63/80] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 |
Date: |
Wed, 14 Apr 2021 13:26:33 +0200 |
when TARGET_AARCH64 is not defined, it is helpful to make
is_aa64() and arm_el_is_aa64 macros defined to "false".
This way we can make more code TARGET_AARCH64-only.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu.h | 37 ++++++++++++++++++++++++-------------
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 99f65c5390..204fc13949 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1053,6 +1053,11 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned
vq);
void aarch64_sve_change_el(CPUARMState *env, int old_el,
int new_el, bool el0_a64);
+static inline bool is_a64(CPUARMState *env)
+{
+ return env->aarch64;
+}
+
/*
* SVE registers are encoded in KVM's memory in an endianness-invariant format.
* The byte at offset i from the start of the in-memory representation contains
@@ -1082,7 +1087,10 @@ static inline void aarch64_sve_narrow_vq(CPUARMState
*env, unsigned vq) { }
static inline void aarch64_sve_change_el(CPUARMState *env, int o,
int n, bool a)
{ }
-#endif
+
+#define is_a64(env) ((void)env, false)
+
+#endif /* TARGET_AARCH64 */
void aarch64_sync_32_to_64(CPUARMState *env);
void aarch64_sync_64_to_32(CPUARMState *env);
@@ -1091,11 +1099,6 @@ int fp_exception_el(CPUARMState *env, int cur_el);
int sve_exception_el(CPUARMState *env, int cur_el);
uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
-static inline bool is_a64(CPUARMState *env)
-{
- return env->aarch64;
-}
-
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@@ -2195,13 +2198,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *env)
}
#endif
-/**
- * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
- * E.g. when in secure state, fields in HCR_EL2 are suppressed,
- * "for all purposes other than a direct read or write access of HCR_EL2."
- * Not included here is HCR_RW.
- */
-uint64_t arm_hcr_el2_eff(CPUARMState *env);
+#ifdef TARGET_AARCH64
/* Return true if the specified exception level is running in AArch64 state. */
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
@@ -2236,6 +2233,20 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int
el)
return aa64;
}
+#else
+
+#define arm_el_is_aa64(env, el) ((void)env, (void)el, false)
+
+#endif /* TARGET_AARCH64 */
+
+/**
+ * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
+ * E.g. when in secure state, fields in HCR_EL2 are suppressed,
+ * "for all purposes other than a direct read or write access of HCR_EL2."
+ * Not included here is HCR_RW.
+ */
+uint64_t arm_hcr_el2_eff(CPUARMState *env);
+
/* Function for determing whether guest cp register reads and writes should
* access the secure or non-secure bank of a cp register. When EL3 is
* operating in AArch32 state, the NS-bit determines whether the secure
--
2.26.2
- [RFC v13 59/80] target/arm: cpu-sve: new module, (continued)
- [RFC v13 59/80] target/arm: cpu-sve: new module, Claudio Fontana, 2021/04/14
- [RFC v13 65/80] target/arm: arch_dump: restrict ELFCLASS64 to AArch64, Claudio Fontana, 2021/04/14
- [RFC v13 62/80] target/arm: cpu-sve: make cpu_sve_finalize_features return bool, Claudio Fontana, 2021/04/14
- [RFC v13 70/80] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve, Claudio Fontana, 2021/04/14
- [RFC v13 69/80] target/arm: tcg-sve: rename the narrow_vq and change_el functions, Claudio Fontana, 2021/04/14
- [RFC v13 72/80] target/arm: cpu-common: wrap a64-only check with is_a64, Claudio Fontana, 2021/04/14
- [RFC v13 77/80] target/arm: cpu64: some final cleanup on aarch64_cpu_finalize_features, Claudio Fontana, 2021/04/14
- [RFC v13 79/80] target/arm: tcg: remove superfluous CONFIG_TCG check, Claudio Fontana, 2021/04/14
- [RFC v13 71/80] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el, Claudio Fontana, 2021/04/14
- [RFC v13 58/80] target/arm: move TCG gt timer creation code in tcg/, Claudio Fontana, 2021/04/14
- [RFC v13 63/80] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64,
Claudio Fontana <=
- [RFC v13 64/80] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64, Claudio Fontana, 2021/04/14
- [RFC v13 74/80] target/arm: cpu-pauth: change arm_cpu_pauth_finalize name and sig, Claudio Fontana, 2021/04/14
- [RFC v13 66/80] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules, Claudio Fontana, 2021/04/14
- [RFC v13 76/80] target/arm: cpu64: rename arm_cpu_finalize_features, Claudio Fontana, 2021/04/14
- [RFC v13 75/80] target/arm: move arm_cpu_finalize_features into cpu64, Claudio Fontana, 2021/04/14
- [RFC v13 73/80] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication, Claudio Fontana, 2021/04/14
- [RFC v13 78/80] XXX target/arm: experiment refactoring cpu "max", Claudio Fontana, 2021/04/14
- [RFC v13 80/80] target/arm: remove v7m stub function for !CONFIG_TCG, Claudio Fontana, 2021/04/14
- [RFC v13 67/80] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64, Claudio Fontana, 2021/04/14
- [RFC v13 68/80] target/arm: tcg-sve: import narrow_vq and change_el functions, Claudio Fontana, 2021/04/14