[Bug 1923197] Re: RISC-V priviledged instruction error

[Alistair Francis]

You can check this by reverting this QEMU commit:

commit d102f19a2085ac931cb998e6153b73248cca49f1
Author: Atish Patra <atish.patra@wdc.com>
Date:   Wed Dec 23 11:25:53 2020 -0800

    target/riscv/pmp: Raise exception if no PMP entry is configured
    
    As per the privilege specification, any access from S/U mode should fail
    if no pmp region is configured.
    
    Signed-off-by: Atish Patra <atish.patra@wdc.com>
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Message-id: 20201223192553.332508-1-atish.patra@wdc.com
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

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https://bugs.launchpad.net/bugs/1923197

Title:
  RISC-V priviledged instruction error

Status in QEMU:
  Invalid

Bug description:
  Hello when performing an MRET with MPP set to something else than 0b11
  in MSTATUS, 'Invalid Instruction' exception will be triggered. The
  problem appeared in code after version 5.2.0. Use following code to
  test.

    # setup interrupt handling for monitor mode
    la t0, entry_loop
    la t1, entry_trap
    li t2, 0x888
    li t3, 0x1880
    csrw mepc, t0
    csrw mtvec, t1
    csrs mie, t2
    csrs mstatus, t3

    # if supervisor mode not supported, then loop forever
    csrr t0, misa
    li t1, 0x40000
    and t2, t1, t0
    beqz t2, 1f

    # setup interrupt i& exception delegation for supervisor mode
    li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
    li t1, 0x1000
    li t2, 0x300
    li t3, 0x222
    csrw mepc, t0
    csrc mstatus, t1
    csrs medeleg, t2
    csrs mideleg, t3

    # pass mhartid as first parameter to supervisor
    csrr a0, mhartid

  1:
    mret

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