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[RFC v14 23/80] target/arm: move sve_zcr_len_for_el to common_cpu
From: |
Claudio Fontana |
Subject: |
[RFC v14 23/80] target/arm: move sve_zcr_len_for_el to common_cpu |
Date: |
Fri, 16 Apr 2021 18:27:27 +0200 |
it is required by arch-dump.c and cpu.c, so apparently
we need this for KVM too
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu-common.c | 43 +++++++++++++++++++++++++++++++++++++++++
target/arm/tcg/helper.c | 33 -------------------------------
2 files changed, 43 insertions(+), 33 deletions(-)
diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c
index 040e06392a..a34f7f19d8 100644
--- a/target/arm/cpu-common.c
+++ b/target/arm/cpu-common.c
@@ -299,3 +299,46 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
return ret;
}
+
+/*
+ * these are AARCH64-only, but due to the chain of dependencies,
+ * between HELPER prototypes, hflags, cpreg definitions and functions in
+ * tcg/ etc, it becomes incredibly messy to add what should be here:
+ *
+ * #ifdef TARGET_AARCH64
+ */
+
+static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
+{
+ uint32_t end_len;
+
+ end_len = start_len &= 0xf;
+ if (!test_bit(start_len, cpu->sve_vq_map)) {
+ end_len = find_last_bit(cpu->sve_vq_map, start_len);
+ assert(end_len < start_len);
+ }
+ return end_len;
+}
+
+/*
+ * Given that SVE is enabled, return the vector length for EL.
+ */
+uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
+{
+ ARMCPU *cpu = env_archcpu(env);
+ uint32_t zcr_len = cpu->sve_max_vq - 1;
+
+ if (el <= 1) {
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
+ }
+ if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
+ }
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
+ }
+
+ return sve_zcr_get_valid_len(cpu, zcr_len);
+}
+
+/* #endif TARGET_AARCH64 , see matching comment above */
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index 4b8a0d436c..5bc0055c87 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -322,39 +322,6 @@ int sve_exception_el(CPUARMState *env, int el)
return 0;
}
-static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
-{
- uint32_t end_len;
-
- end_len = start_len &= 0xf;
- if (!test_bit(start_len, cpu->sve_vq_map)) {
- end_len = find_last_bit(cpu->sve_vq_map, start_len);
- assert(end_len < start_len);
- }
- return end_len;
-}
-
-/*
- * Given that SVE is enabled, return the vector length for EL.
- */
-uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
-{
- ARMCPU *cpu = env_archcpu(env);
- uint32_t zcr_len = cpu->sve_max_vq - 1;
-
- if (el <= 1) {
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
- }
- if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
- }
- if (arm_feature(env, ARM_FEATURE_EL3)) {
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
- }
-
- return sve_zcr_get_valid_len(cpu, zcr_len);
-}
-
void hw_watchpoint_update(ARMCPU *cpu, int n)
{
CPUARMState *env = &cpu->env;
--
2.26.2
- [RFC v14 13/80] target/arm: fix style in preparation of new cpregs module, (continued)
- [RFC v14 13/80] target/arm: fix style in preparation of new cpregs module, Claudio Fontana, 2021/04/16
- [RFC v14 19/80] target/arm: add temporary stub for arm_rebuild_hflags, Claudio Fontana, 2021/04/16
- [RFC v14 12/80] target/arm: move physical address translation to cpu-mmu, Claudio Fontana, 2021/04/16
- [RFC v14 18/80] target/arm: move cpsr_read, cpsr_write to cpu_common, Claudio Fontana, 2021/04/16
- [RFC v14 22/80] target/arm: move arm_mmu_idx* to cpu-mmu, Claudio Fontana, 2021/04/16
- [RFC v14 21/80] target/arm: split vfp state setting from tcg helpers, Claudio Fontana, 2021/04/16
- [RFC v14 24/80] target/arm: move arm_sctlr away from tcg helpers, Claudio Fontana, 2021/04/16
- [RFC v14 14/80] target/arm: split cpregs from tcg/helper.c, Claudio Fontana, 2021/04/16
- [RFC v14 23/80] target/arm: move sve_zcr_len_for_el to common_cpu,
Claudio Fontana <=
- [RFC v14 20/80] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu, Claudio Fontana, 2021/04/16
- [RFC v14 26/80] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code, Claudio Fontana, 2021/04/16
- [RFC v14 27/80] target/arm: new cpu32 ARM 32 bit CPU Class, Claudio Fontana, 2021/04/16
- [RFC v14 28/80] target/arm: split 32bit and 64bit arm dump state, Claudio Fontana, 2021/04/16
- [RFC v14 29/80] target/arm: move a15 cpu model away from the TCG-only models, Claudio Fontana, 2021/04/16
- [RFC v14 25/80] target/arm: move arm_cpu_list to common_cpu, Claudio Fontana, 2021/04/16
- [RFC v14 32/80] target/arm: fix comments style of fp_exception_el before moving it, Claudio Fontana, 2021/04/16
- [RFC v14 33/80] target/arm: move fp_exception_el out of TCG helpers, Claudio Fontana, 2021/04/16
- [RFC v14 38/80] target/arm: rename handle_semihosting to tcg_handle_semihosting, Claudio Fontana, 2021/04/16
- [RFC v14 42/80] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Claudio Fontana, 2021/04/16