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[PATCH v5 16/17] target/riscv: rvb: support and turn on B-extension from
From: |
frank . chang |
Subject: |
[PATCH v5 16/17] target/riscv: rvb: support and turn on B-extension from command line |
Date: |
Wed, 21 Apr 2021 12:13:58 +0800 |
From: Kito Cheng <kito.cheng@sifive.com>
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 4 ++++
target/riscv/cpu.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b6..8464a152d14 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -473,6 +473,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
+ if (cpu->cfg.ext_b) {
+ target_misa |= RVB;
+ }
if (cpu->cfg.ext_v) {
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
@@ -543,6 +546,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
+ DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0a33d387ba8..97073bb8e27 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -72,6 +72,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVB RV('B')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -288,6 +289,7 @@ struct RISCVCPU {
bool ext_f;
bool ext_d;
bool ext_c;
+ bool ext_b;
bool ext_s;
bool ext_u;
bool ext_h;
--
2.17.1
- [PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions, (continued)
- [PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions, frank . chang, 2021/04/21
- [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions, frank . chang, 2021/04/21
- [PATCH v5 09/17] target/riscv: rvb: single-bit instructions, frank . chang, 2021/04/21
- [PATCH v5 10/17] target/riscv: rvb: shift ones, frank . chang, 2021/04/21
- [PATCH v5 11/17] target/riscv: rvb: rotate (left/right), frank . chang, 2021/04/21
- [PATCH v5 12/17] target/riscv: rvb: generalized reverse, frank . chang, 2021/04/21
- [PATCH v5 13/17] target/riscv: rvb: generalized or-combine, frank . chang, 2021/04/21
- [PATCH v5 14/17] target/riscv: rvb: address calculation, frank . chang, 2021/04/21
- [PATCH v5 15/17] target/riscv: rvb: add/shift with prefix zero-extend, frank . chang, 2021/04/21
- [PATCH v5 16/17] target/riscv: rvb: support and turn on B-extension from command line,
frank . chang <=
- [PATCH v5 17/17] target/riscv: rvb: add b-ext version cpu option, frank . chang, 2021/04/21