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Re: [PATCH v5 06/17] target/riscv: rvb: min/max instructions
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v5 06/17] target/riscv: rvb: min/max instructions |
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Date: |
Tue, 27 Apr 2021 16:06:04 +1000 |
On Wed, Apr 21, 2021 at 2:19 PM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 4 ++++
> target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
> 2 files changed, 28 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 7f32b8c6d15..d64326fd864 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -605,3 +605,7 @@ xnor 0100000 .......... 100 ..... 0110011 @r
> pack 0000100 .......... 100 ..... 0110011 @r
> packu 0100100 .......... 100 ..... 0110011 @r
> packh 0000100 .......... 111 ..... 0110011 @r
> +min 0000101 .......... 100 ..... 0110011 @r
> +minu 0000101 .......... 101 ..... 0110011 @r
> +max 0000101 .......... 110 ..... 0110011 @r
> +maxu 0000101 .......... 111 ..... 0110011 @r
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index 2d24dafac09..2aa4515fe31 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -71,6 +71,30 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
> return gen_arith(ctx, a, gen_packh);
> }
>
> +static bool trans_min(DisasContext *ctx, arg_min *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, tcg_gen_smin_tl);
> +}
> +
> +static bool trans_max(DisasContext *ctx, arg_max *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, tcg_gen_smax_tl);
> +}
> +
> +static bool trans_minu(DisasContext *ctx, arg_minu *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, tcg_gen_umin_tl);
> +}
> +
> +static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, tcg_gen_umax_tl);
> +}
> +
> /* RV64-only instructions */
> #ifdef TARGET_RISCV64
>
> --
> 2.17.1
>
>
- [PATCH v5 01/17] target/riscv: reformat @sh format encoding for B-extension, (continued)
- [PATCH v5 01/17] target/riscv: reformat @sh format encoding for B-extension, frank . chang, 2021/04/21
- [PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros, frank . chang, 2021/04/21
- [PATCH v5 04/17] target/riscv: rvb: logic-with-negate, frank . chang, 2021/04/21
- [PATCH v5 03/17] target/riscv: rvb: count bits set, frank . chang, 2021/04/21
- [PATCH v5 05/17] target/riscv: rvb: pack two words into one register, frank . chang, 2021/04/21
- [PATCH v5 06/17] target/riscv: rvb: min/max instructions, frank . chang, 2021/04/21
- Re: [PATCH v5 06/17] target/riscv: rvb: min/max instructions,
Alistair Francis <=
- [PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions, frank . chang, 2021/04/21
- [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions, frank . chang, 2021/04/21
- [PATCH v5 09/17] target/riscv: rvb: single-bit instructions, frank . chang, 2021/04/21
- [PATCH v5 10/17] target/riscv: rvb: shift ones, frank . chang, 2021/04/21
- [PATCH v5 11/17] target/riscv: rvb: rotate (left/right), frank . chang, 2021/04/21
- [PATCH v5 12/17] target/riscv: rvb: generalized reverse, frank . chang, 2021/04/21
- [PATCH v5 13/17] target/riscv: rvb: generalized or-combine, frank . chang, 2021/04/21
- [PATCH v5 14/17] target/riscv: rvb: address calculation, frank . chang, 2021/04/21
- [PATCH v5 15/17] target/riscv: rvb: add/shift with prefix zero-extend, frank . chang, 2021/04/21