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[PULL 03/51] hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' su
From: |
Peter Maydell |
Subject: |
[PULL 03/51] hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffix |
Date: |
Wed, 1 Sep 2021 11:36:05 +0100 |
From: Philippe Mathieu-Daudé <philmd@redhat.com>
QEMU load/store API (docs/devel/loads-stores.rst) uses the 'q'
suffix for 64-bit accesses. Rename the current 'll' suffix to
have the GIC dist accessors better match the rest of the codebase.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20210826180704.2131949-2-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_dist.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index b65f56f9035..7e9b393d9ab 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -763,8 +763,8 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr offset,
}
}
-static MemTxResult gicd_writell(GICv3State *s, hwaddr offset,
- uint64_t value, MemTxAttrs attrs)
+static MemTxResult gicd_writeq(GICv3State *s, hwaddr offset,
+ uint64_t value, MemTxAttrs attrs)
{
/* Our only 64-bit registers are GICD_IROUTER<n> */
int irq;
@@ -779,8 +779,8 @@ static MemTxResult gicd_writell(GICv3State *s, hwaddr
offset,
}
}
-static MemTxResult gicd_readll(GICv3State *s, hwaddr offset,
- uint64_t *data, MemTxAttrs attrs)
+static MemTxResult gicd_readq(GICv3State *s, hwaddr offset,
+ uint64_t *data, MemTxAttrs attrs)
{
/* Our only 64-bit registers are GICD_IROUTER<n> */
int irq;
@@ -812,7 +812,7 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset,
uint64_t *data,
r = gicd_readl(s, offset, data, attrs);
break;
case 8:
- r = gicd_readll(s, offset, data, attrs);
+ r = gicd_readq(s, offset, data, attrs);
break;
default:
r = MEMTX_ERROR;
@@ -854,7 +854,7 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset,
uint64_t data,
r = gicd_writel(s, offset, data, attrs);
break;
case 8:
- r = gicd_writell(s, offset, data, attrs);
+ r = gicd_writeq(s, offset, data, attrs);
break;
default:
r = MEMTX_ERROR;
--
2.20.1
- [PULL 00/51] target-arm queue, Peter Maydell, 2021/09/01
- [PULL 02/51] hw/arm/raspi: Remove deprecated raspi2/raspi3 aliases, Peter Maydell, 2021/09/01
- [PULL 05/51] hw: Add compat machines for 6.2, Peter Maydell, 2021/09/01
- [PULL 01/51] tests: Remove uses of deprecated raspi2/raspi3 machine names, Peter Maydell, 2021/09/01
- [PULL 07/51] target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM, Peter Maydell, 2021/09/01
- [PULL 08/51] target/arm: Implement MVE VCADD, Peter Maydell, 2021/09/01
- [PULL 03/51] hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffix,
Peter Maydell <=
- [PULL 04/51] hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans, Peter Maydell, 2021/09/01
- [PULL 12/51] target/arm: Implement MVE scalar fp insns, Peter Maydell, 2021/09/01
- [PULL 10/51] target/arm: Implement MVE VCMUL and VCMLA, Peter Maydell, 2021/09/01
- [PULL 09/51] target/arm: Implement MVE VFMA and VFMS, Peter Maydell, 2021/09/01
- [PULL 21/51] target/arm: Implement MVE VCVT between single and half precision, Peter Maydell, 2021/09/01
- [PULL 11/51] target/arm: Implement MVE VMAXNMA and VMINNMA, Peter Maydell, 2021/09/01
- [PULL 17/51] target/arm: Implement MVE fp scalar comparisons, Peter Maydell, 2021/09/01
- [PULL 18/51] target/arm: Implement MVE VCVT between floating and fixed point, Peter Maydell, 2021/09/01
- [PULL 27/51] arm: Move M-profile RAS register block into its own device, Peter Maydell, 2021/09/01
- [PULL 31/51] hw/timer/armv7m_systick: Add input clocks, Peter Maydell, 2021/09/01