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[PULL 14/51] softfloat: Remove assertion preventing silencing of NaN in
From: |
Peter Maydell |
Subject: |
[PULL 14/51] softfloat: Remove assertion preventing silencing of NaN in default-NaN mode |
Date: |
Wed, 1 Sep 2021 11:36:16 +0100 |
In commit a777d6033447a we added an assertion to parts_silence_nan() that
prohibits calling float*_silence_nan() when in default-NaN mode.
This ties together a property of the output ("do we generate a default
NaN when the result is a NaN?") with an operation on an input ("silence
this input NaN").
It's true that most of the time when in default-NaN mode you won't
need to silence an input NaN, because you can just produce the
default NaN as the result instead. But some functions like
float*_maxnum() are defined to be able to work with quiet NaNs, so
silencing an input SNaN is still reasonable. In particular, the
upcoming implementation of MVE VMAXNMV would fall over this assertion
if we didn't delete it.
Delete the assertion.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
fpu/softfloat-specialize.c.inc | 1 -
1 file changed, 1 deletion(-)
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index 12467bb9bba..f2ad0f335e6 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -198,7 +198,6 @@ static void parts128_default_nan(FloatParts128 *p,
float_status *status)
static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status)
{
g_assert(!no_signaling_nans(status));
- g_assert(!status->default_nan_mode);
/* The only snan_bit_is_one target without default_nan_mode is HPPA. */
if (snan_bit_is_one(status)) {
--
2.20.1
- [PULL 10/51] target/arm: Implement MVE VCMUL and VCMLA, (continued)
- [PULL 10/51] target/arm: Implement MVE VCMUL and VCMLA, Peter Maydell, 2021/09/01
- [PULL 09/51] target/arm: Implement MVE VFMA and VFMS, Peter Maydell, 2021/09/01
- [PULL 21/51] target/arm: Implement MVE VCVT between single and half precision, Peter Maydell, 2021/09/01
- [PULL 11/51] target/arm: Implement MVE VMAXNMA and VMINNMA, Peter Maydell, 2021/09/01
- [PULL 17/51] target/arm: Implement MVE fp scalar comparisons, Peter Maydell, 2021/09/01
- [PULL 18/51] target/arm: Implement MVE VCVT between floating and fixed point, Peter Maydell, 2021/09/01
- [PULL 27/51] arm: Move M-profile RAS register block into its own device, Peter Maydell, 2021/09/01
- [PULL 31/51] hw/timer/armv7m_systick: Add input clocks, Peter Maydell, 2021/09/01
- [PULL 13/51] target/arm: Implement MVE fp-with-scalar VFMA, VFMAS, Peter Maydell, 2021/09/01
- [PULL 15/51] target/arm: Implement MVE FP max/min across vector, Peter Maydell, 2021/09/01
- [PULL 14/51] softfloat: Remove assertion preventing silencing of NaN in default-NaN mode,
Peter Maydell <=
- [PULL 22/51] target/arm: Implement MVE VRINT insns, Peter Maydell, 2021/09/01
- [PULL 06/51] target/arm: Implement MVE VADD (floating-point), Peter Maydell, 2021/09/01
- [PULL 20/51] target/arm: Implement MVE VCVT with specified rounding mode, Peter Maydell, 2021/09/01
- [PULL 24/51] target-arm: Add support for Fujitsu A64FX, Peter Maydell, 2021/09/01
- [PULL 16/51] target/arm: Implement MVE fp vector comparisons, Peter Maydell, 2021/09/01
- [PULL 19/51] target/arm: Implement MVE VCVT between fp and integer, Peter Maydell, 2021/09/01
- [PULL 33/51] armsse: Wire up systick cpuclk clock, Peter Maydell, 2021/09/01
- [PULL 30/51] hw/timer/armv7m_systick: Add usual QEMU interface comment, Peter Maydell, 2021/09/01
- [PULL 36/51] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize, Peter Maydell, 2021/09/01
- [PULL 39/51] hw/arm/stm32f405: Wire up sysclk and refclk, Peter Maydell, 2021/09/01