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[PATCH v3 6/9] escc: implement hard reset as described in the datasheet
From: |
Mark Cave-Ayland |
Subject: |
[PATCH v3 6/9] escc: implement hard reset as described in the datasheet |
Date: |
Fri, 3 Sep 2021 12:32:20 +0100 |
The hardware reset differs from a device reset in that it only changes the
contents
of specific registers. Remove the code that resets all the registers to zero
during
hardware reset and implement the default values using the existing soft reset
code
with the additional changes listed in the table in the "Z85C30 Reset" section.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/char/escc.c | 41 +++++++++++++----------------------------
1 file changed, 13 insertions(+), 28 deletions(-)
diff --git a/hw/char/escc.c b/hw/char/escc.c
index d5c7136e97..80f1d1b8fc 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -118,6 +118,8 @@
#define W_SYNC2 7
#define W_TXBUF 8
#define W_MINTR 9
+#define MINTR_VIS 0x01
+#define MINTR_NV 0x02
#define MINTR_STATUSHI 0x10
#define MINTR_SOFTIACK 0x20
#define MINTR_RST_MASK 0xc0
@@ -347,36 +349,19 @@ static void escc_soft_reset_chn(ESCCChannelState *s)
static void escc_hard_reset_chn(ESCCChannelState *s)
{
- int i;
+ escc_soft_reset_chn(s);
- s->reg = 0;
- for (i = 0; i < ESCC_SERIAL_REGS; i++) {
- s->rregs[i] = 0;
- s->wregs[i] = 0;
- }
- /* 1X divisor, 1 stop bit, no parity */
- s->wregs[W_TXCTRL1] = TXCTRL1_1STOP;
- s->wregs[W_MINTR] = MINTR_RST_ALL;
- /* Synch mode tx clock = TRxC */
+ /*
+ * Hard reset is almost identical to soft reset above, except that the
+ * values of WR9 (W_MINTR), WR10 (W_MISC1), WR11 (W_CLOCK) and WR14
+ * (W_MISC2) have extra bits forced to 0/1
+ */
+ s->wregs[W_MINTR] &= MINTR_VIS | MINTR_NV;
+ s->wregs[W_MINTR] |= MINTR_RST_B | MINTR_RST_A;
+ s->wregs[W_MISC1] = 0;
s->wregs[W_CLOCK] = CLOCK_TRXC;
- /* PLL disabled */
- s->wregs[W_MISC2] = MISC2_PLLDIS;
- /* Enable most interrupts */
- s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |
- EXTINT_TXUNDRN | EXTINT_BRKINT;
- if (s->disabled) {
- s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC |
- STATUS_CTS | STATUS_TXUNDRN;
- } else {
- s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN;
- }
- s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT;
-
- s->rx = s->tx = 0;
- s->rxint = s->txint = 0;
- s->rxint_under_svc = s->txint_under_svc = 0;
- s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0;
- clear_queue(s);
+ s->wregs[W_MISC2] &= MISC2_PLLCMD1 | MISC2_PLLCMD2;
+ s->wregs[W_MISC2] |= MISC2_LCL_LOOP | MISC2_PLLCMD0;
}
static void escc_reset(DeviceState *d)
--
2.20.1
- [PATCH v3 0/9] escc: fix reset and R_STATUS when SDLC mode is enabled, Mark Cave-Ayland, 2021/09/03
- [PATCH v3 2/9] escc: reset register values to zero in escc_reset(), Mark Cave-Ayland, 2021/09/03
- [PATCH v3 1/9] escc: checkpatch fixes, Mark Cave-Ayland, 2021/09/03
- [PATCH v3 3/9] escc: introduce escc_soft_reset_chn() for software reset, Mark Cave-Ayland, 2021/09/03
- [PATCH v3 4/9] escc: introduce escc_hard_reset_chn() for hardware reset, Mark Cave-Ayland, 2021/09/03
- [PATCH v3 6/9] escc: implement hard reset as described in the datasheet,
Mark Cave-Ayland <=
- [PATCH v3 5/9] escc: implement soft reset as described in the datasheet, Mark Cave-Ayland, 2021/09/03
- [PATCH v3 7/9] escc: remove register changes from escc_reset_chn(), Mark Cave-Ayland, 2021/09/03
- [PATCH v3 8/9] escc: re-use escc_reset_chn() for soft reset, Mark Cave-Ayland, 2021/09/03
- [PATCH v3 9/9] escc: fix STATUS_SYNC bit in R_STATUS register, Mark Cave-Ayland, 2021/09/03
- Re: [PATCH v3 0/9] escc: fix reset and R_STATUS when SDLC mode is enabled, Mark Cave-Ayland, 2021/09/08