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[PATCH v9 03/14] target/riscv: slli.uw is only a valid encoding if shamt
From: |
Philipp Tomsich |
Subject: |
[PATCH v9 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits |
Date: |
Fri, 3 Sep 2021 19:00:49 +0200 |
For RV64, the shamt field in slli.uw is 6 bits wide. While the encoding
space currently reserves a wider shamt-field (for use is a future RV128
ISA), setting the additional bit to 1 will not map to slli.uw for RV64
and needs to be treated as an illegal instruction.
Note that this encoding being reserved for a future RV128 does not imply
that no other instructions for RV64-only could be added in this encoding
space in the future.
As the implementation is separate from the gen_shifti helpers, we keep
it that way and add the check for the shamt-width here.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v9:
- Rebased to 8880cc4362.
Changes in v3:
- Instead of defining a new decoding format, we treat slli.uw as if it
had a 7bit-wide field for shamt (the 7th bit is reserved for RV128)
and check for validity of the encoding in C code.
target/riscv/insn_trans/trans_rvb.c.inc | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 91da7c5853..77114889de 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -652,5 +652,15 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw
*a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBA(ctx);
+
+ /*
+ * The shamt field is only 6 bits for RV64 (with the 7th bit
+ * remaining reserved for RV128). If the reserved bit is set
+ * on RV64, the encoding is illegal.
+ */
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
}
--
2.25.1
- [PATCH v9 00/14] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/09/03
- [PATCH v9 02/14] target/riscv: Reassign instructions to the Zba-extension, Philipp Tomsich, 2021/09/03
- [PATCH v9 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Philipp Tomsich, 2021/09/03
- [PATCH v9 06/14] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/09/03
- [PATCH v9 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/09/03
- [PATCH v9 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits,
Philipp Tomsich <=
- [PATCH v9 08/14] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/03
- [PATCH v9 11/14] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/09/03
- [PATCH v9 07/14] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/09/03
- [PATCH v9 04/14] target/riscv: Remove the W-form instructions from Zbs, Philipp Tomsich, 2021/09/03
- [PATCH v9 01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/09/03
- [PATCH v9 10/14] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/09/03
- [PATCH v9 12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Philipp Tomsich, 2021/09/03
- [PATCH v9 13/14] target/riscv: Remove RVB (replaced by Zb[abcs], Philipp Tomsich, 2021/09/03