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Re: [PATCH v2 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM
From: |
Peter Maydell |
Subject: |
Re: [PATCH v2 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM |
Date: |
Tue, 7 Sep 2021 16:24:07 +0100 |
On Mon, 23 Aug 2021 at 18:49, Tong Ho <tong.ho@xilinx.com> wrote:
>
> This series implements the Xilinx eFUSE and BBRAM devices for
> the Versal and ZynqMP product families.
>
> Furthermore, both new devices are connected to the xlnx-versal-virt
> board and the xlnx-zcu102 board.
>
> See changes in docs/system/arm/xlnx-versal-virt.rst for detail.
>
> ---
Hi; I've reviewed the first few patches. Some of those comments
will apply also to the other device model patches that I haven't
looked at in detail, and the changing of the block backend handling
so the board creates those rather than the device will mean that
the later patches are also affected. So I'll let you work through
those review comments and review the rest in more detail when you
post a v3.
thanks
-- PMM
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