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[RFC PATCH 4/5] target/i386: Define specific PT feature set for IceLake-
From: |
Xiaoyao Li |
Subject: |
[RFC PATCH 4/5] target/i386: Define specific PT feature set for IceLake-server and Snowridge |
Date: |
Thu, 9 Sep 2021 22:41:49 +0800 |
For IceLake-server, it's just the same as using the default PT
feature set since the default one is exact taken from ICX.
For Snowridge, define it according to real SNR silicon capabilities.
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
target/i386/cpu.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 00c4ad23110d..2b50ccf79b92 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3383,6 +3383,15 @@ static const X86CPUDefinition builtin_x86_defs[] = {
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
/* Missing: Mode-based execute control (XS/XU), processor tracing, TSC
scaling */
+ .has_specific_intel_pt_feature_set = true,
+ .features[FEAT_14_0_EBX] =
+ CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB |
+ CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC,
+ .features[FEAT_14_0_ECX] =
+ CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES |
+ CPUID_14_0_ECX_SINGLE_RANGE,
+ .features[FEAT_14_1_EAX] = 0x249 << 16 | 0x2,
+ .features[FEAT_14_1_EBX] = 0x003f << 16 | 0x1fff,
.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
MSR_VMX_BASIC_TRUE_CTLS,
.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
@@ -3652,6 +3661,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
+ .has_specific_intel_pt_feature_set = true,
+ .features[FEAT_14_0_EBX] =
+ CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB |
+ CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC |
+ CPUID_14_0_EBX_PTWRITE | CPUID_14_0_EBX_POWER_EVENT |
+ CPUID_14_0_EBX_PSB_PMI_PRESERVATION,
+ .features[FEAT_14_0_ECX] =
+ CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES |
+ CPUID_14_0_ECX_SINGLE_RANGE | CPUID_14_0_ECX_LIP,
+ .features[FEAT_14_1_EAX] = 0x249 << 16 | 0x2,
+ .features[FEAT_14_1_EBX] = 0x003f << 16 | 0xffff,
.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
MSR_VMX_BASIC_TRUE_CTLS,
.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
--
2.27.0
- [RFC PATCH 0/5] Make Intel PT configurable, Xiaoyao Li, 2021/09/09
- [RFC PATCH 2/5] target/i386: Introduce FeatureWordInfo for Intel PT CPUID leaf 0xD, Xiaoyao Li, 2021/09/09
- [RFC PATCH 3/5] target/i386: Enable host pass through of Intel PT, Xiaoyao Li, 2021/09/09
- [RFC PATCH 4/5] target/i386: Define specific PT feature set for IceLake-server and Snowridge,
Xiaoyao Li <=
- [RFC PATCH 5/5] target/i386: Access MSR_IA32_RTIT_ADDRn based on guest CPUID configuration, Xiaoyao Li, 2021/09/09
- [RFC PATCH 1/5] target/i386: Print CPUID subleaf info for unsupported feature, Xiaoyao Li, 2021/09/09
- Re: [RFC PATCH 0/5] Make Intel PT configurable, Xiaoyao Li, 2021/09/26