Re: [PATCH v2 09/12] target/arm: Optimize MVE VSHL, VSHR immediate forms

[Richard Henderson]

On 9/16/21 3:01 AM, Peter Maydell wrote:
> On Mon, 13 Sept 2021 at 16:53, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> > On 9/13/21 7:21 AM, Peter Maydell wrote:
> > > On Mon, 13 Sept 2021 at 14:56, Richard Henderson
> > > <richard.henderson@linaro.org> wrote:
> > > > On 9/13/21 2:54 AM, Peter Maydell wrote:
> > > > > +static void do_gvec_shri_s(unsigned vece, uint32_t dofs, uint32_t aofs,
> > > > > +                           int64_t shift, uint32_t oprsz, uint32_t maxsz)
> > > > > +{
> > > > > +    /*
> > > > > +     * We get here with a negated shift count, and we must handle
> > > > > +     * shifts by the element size, which tcg_gen_gvec_sari() does not do.
> > > > > +     */
> > > > > +    shift = -shift;
> > > >
> > > > You've already performed the negation in do_2shift_vec.
> > >
> > > Here we are undoing the negation we did there, so as to get a
> > > "positive means shift right" shift count back again, which is what
> > > the instruction encoding has and what tcg_gen_gvic_shri() wants.
> >
> > Ah, I misinterpreted.
> >
> > > > Perhaps worth placing these functions somewhere we can share code with NEON?  
> > > > Tactical
> > > > error, perhaps, open-coding these tests in trans_VSHR_S_2sh and 
> > > > trans_VSHR_U_2sh.
> > >
> > > I'm not convinced the resemblance is close enough to be worth the
> > > effort...
> >
> > Yeah, not with the negation bit above.
>
> Could I get a reviewed-by for this patch, then, please ?

Oops, yes.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~