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Re: [PATCH v2 05/41] configure: Merge riscv32 and riscv64 host architect
From: |
Alistair Francis |
Subject: |
Re: [PATCH v2 05/41] configure: Merge riscv32 and riscv64 host architectures |
Date: |
Mon, 20 Sep 2021 08:57:10 +1000 |
On Sun, Sep 19, 2021 at 4:53 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The existing code for safe-syscall.inc.S will compile
> without change for riscv32 and riscv64. We may also
> drop the meson.build stanza that merges them for tcg/.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> configure | 8 ++------
> meson.build | 4 +---
> linux-user/host/{riscv64 => riscv}/hostdep.h | 4 ++--
> linux-user/host/riscv32/hostdep.h | 11 -----------
> linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S | 0
> 5 files changed, 5 insertions(+), 22 deletions(-)
> rename linux-user/host/{riscv64 => riscv}/hostdep.h (94%)
> delete mode 100644 linux-user/host/riscv32/hostdep.h
> rename linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S (100%)
>
> diff --git a/configure b/configure
> index da2501489f..6ff037bac1 100755
> --- a/configure
> +++ b/configure
> @@ -650,11 +650,7 @@ elif check_define __s390__ ; then
> cpu="s390"
> fi
> elif check_define __riscv ; then
> - if check_define _LP64 ; then
> - cpu="riscv64"
> - else
> - cpu="riscv32"
> - fi
> + cpu="riscv"
> elif check_define __arm__ ; then
> cpu="arm"
> elif check_define __aarch64__ ; then
> @@ -667,7 +663,7 @@ ARCH=
> # Normalise host CPU name and set ARCH.
> # Note that this case should only have supported host CPUs, not guests.
> case "$cpu" in
> - ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64)
> + ppc|ppc64|s390x|sparc64|x32|riscv)
> ;;
> ppc64le)
> ARCH="ppc64"
> diff --git a/meson.build b/meson.build
> index 2711cbb789..c35a230bf0 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -56,7 +56,7 @@ have_block = have_system or have_tools
> python = import('python').find_installation()
>
> supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin',
> 'sunos', 'linux']
> -supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86',
> 'x86_64',
> +supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64',
> 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64']
>
> cpu = host_machine.cpu_family()
> @@ -271,8 +271,6 @@ if not get_option('tcg').disabled()
> tcg_arch = 'i386'
> elif config_host['ARCH'] == 'ppc64'
> tcg_arch = 'ppc'
> - elif config_host['ARCH'] in ['riscv32', 'riscv64']
> - tcg_arch = 'riscv'
> endif
> add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' /
> tcg_arch,
> language: ['c', 'cpp', 'objc'])
> diff --git a/linux-user/host/riscv64/hostdep.h
> b/linux-user/host/riscv/hostdep.h
> similarity index 94%
> rename from linux-user/host/riscv64/hostdep.h
> rename to linux-user/host/riscv/hostdep.h
> index 865f0fb9ff..2ba07456ae 100644
> --- a/linux-user/host/riscv64/hostdep.h
> +++ b/linux-user/host/riscv/hostdep.h
> @@ -5,8 +5,8 @@
> * See the COPYING file in the top-level directory.
> */
>
> -#ifndef RISCV64_HOSTDEP_H
> -#define RISCV64_HOSTDEP_H
> +#ifndef RISCV_HOSTDEP_H
> +#define RISCV_HOSTDEP_H
>
> /* We have a safe-syscall.inc.S */
> #define HAVE_SAFE_SYSCALL
> diff --git a/linux-user/host/riscv32/hostdep.h
> b/linux-user/host/riscv32/hostdep.h
> deleted file mode 100644
> index adf9edbf2d..0000000000
> --- a/linux-user/host/riscv32/hostdep.h
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -/*
> - * hostdep.h : things which are dependent on the host architecture
> - *
> - * This work is licensed under the terms of the GNU GPL, version 2 or later.
> - * See the COPYING file in the top-level directory.
> - */
> -
> -#ifndef RISCV32_HOSTDEP_H
> -#define RISCV32_HOSTDEP_H
> -
> -#endif
> diff --git a/linux-user/host/riscv64/safe-syscall.inc.S
> b/linux-user/host/riscv/safe-syscall.inc.S
> similarity index 100%
> rename from linux-user/host/riscv64/safe-syscall.inc.S
> rename to linux-user/host/riscv/safe-syscall.inc.S
> --
> 2.25.1
>
>
- [PATCH v2 00/41] linux-user: Streamline handling of SIGSEGV, Richard Henderson, 2021/09/18
- [PATCH v2 01/41] accel/tcg: Split out adjust_signal_pc, Richard Henderson, 2021/09/18
- [PATCH v2 03/41] accel/tcg: Split out handle_sigsegv_accerr_write, Richard Henderson, 2021/09/18
- [PATCH v2 02/41] accel/tcg: Move clear_helper_retaddr to cpu loop, Richard Henderson, 2021/09/18
- [PATCH v2 05/41] configure: Merge riscv32 and riscv64 host architectures, Richard Henderson, 2021/09/18
- [PATCH v2 04/41] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller, Richard Henderson, 2021/09/18
- [PATCH v2 08/41] linux-user/host/ppc: Populate host_signal.h, Richard Henderson, 2021/09/18
- [PATCH v2 06/41] linux-user: Reorg handling for SIGSEGV, Richard Henderson, 2021/09/18
- [PATCH v2 10/41] linux-user/host/sparc: Populate host_signal.h, Richard Henderson, 2021/09/18
- [PATCH v2 07/41] linux-user/host/x86: Populate host_signal.h, Richard Henderson, 2021/09/18
- [PATCH v2 09/41] linux-user/host/alpha: Populate host_signal.h, Richard Henderson, 2021/09/18