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Re: [PULL 00/21] riscv-to-apply queue
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From: |
Peter Maydell |
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Subject: |
Re: [PULL 00/21] riscv-to-apply queue |
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Date: |
Mon, 20 Sep 2021 14:19:07 +0100 |
On Thu, 16 Sept 2021 at 22:49, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit d1fe59377bbbf91dfded1f08ffe3c636e9db8dc0:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/trivial-branch-for-6.2-pull-request' into staging
> (2021-09-16 16:02:31 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210917
>
> for you to fetch changes up to c14620db9b66de88bb4fef1d0cfc283bb3d53f85:
>
> hw/riscv: opentitan: Correct the USB Dev address (2021-09-17 07:43:55 +1000)
>
> ----------------------------------------------------------------
> Second RISC-V PR for QEMU 6.2
>
> - ePMP CSR address updates
> - Convert internal interrupts to use QEMU GPIO lines
> - SiFive PWM support
> - Support for RISC-V ACLINT
> - SiFive PDMA fixes
> - Update to u-boot instructions for sifive_u
> - mstatus.SD bug fix for hypervisor extensions
> - OpenTitan fix for USB dev address
>
Hi; this fails to build on clang:
../../target/riscv/cpu_helper.c:109:64: error: implicit conversion
from 'unsigned long long' to 'target_ulong' (aka 'unsigned int')
changes value from 9223372036854775808 to 0
[-Werror,-Wconstant-conversion]
target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
~~ ^~~~~~~~~~~~
../../target/riscv/cpu_bits.h:362:29: note: expanded from macro 'MSTATUS64_SD'
#define MSTATUS64_SD 0x8000000000000000ULL
^~~~~~~~~~~~~~~~~~~~~
1 error generated.
thanks
-- PMM
- [PULL 12/21] hw/riscv: virt: Re-factor FDT generation, (continued)
- [PULL 12/21] hw/riscv: virt: Re-factor FDT generation, Alistair Francis, 2021/09/16
- [PULL 14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set, Alistair Francis, 2021/09/16
- [PULL 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions, Alistair Francis, 2021/09/16
- [PULL 13/21] hw/riscv: virt: Add optional ACLINT support to virt machine, Alistair Francis, 2021/09/16
- [PULL 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions, Alistair Francis, 2021/09/16
- [PULL 17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer, Alistair Francis, 2021/09/16
- [PULL 18/21] docs/system/riscv: sifive_u: Update U-Boot instructions, Alistair Francis, 2021/09/16
- [PULL 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped, Alistair Francis, 2021/09/16
- [PULL 20/21] target/riscv: csr: Rename HCOUNTEREN_CY and friends, Alistair Francis, 2021/09/16
- [PULL 21/21] hw/riscv: opentitan: Correct the USB Dev address, Alistair Francis, 2021/09/16
- Re: [PULL 00/21] riscv-to-apply queue,
Peter Maydell <=