Re: [PULL v2 00/21] riscv-to-apply queue

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Re: [PULL v2 00/21] riscv-to-apply queue

From:	Richard Henderson
Subject:	Re: [PULL v2 00/21] riscv-to-apply queue
Date:	Tue, 21 Sep 2021 13:49:22 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 9/20/21 11:53 PM, Alistair Francis wrote:

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 326ff8dd09556fc2e257196c49f35009700794ac:

   Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into 
staging (2021-09-20 16:17:05 +0100)

are available in the Git repository at:

   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210921

for you to fetch changes up to ed481d9837250aa682f5156528bc923e1b214f76:

   hw/riscv: opentitan: Correct the USB Dev address (2021-09-21 12:10:47 +1000)

----------------------------------------------------------------
Second RISC-V PR for QEMU 6.2

  - ePMP CSR address updates
  - Convert internal interrupts to use QEMU GPIO lines
  - SiFive PWM support
  - Support for RISC-V ACLINT
  - SiFive PDMA fixes
  - Update to u-boot instructions for sifive_u
  - mstatus.SD bug fix for hypervisor extensions
  - OpenTitan fix for USB dev address


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.2
for any user-visible changes.

r~

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[PULL v2 12/21] hw/riscv: virt: Re-factor FDT generation, (continued)
- [PULL v2 12/21] hw/riscv: virt: Re-factor FDT generation, Alistair Francis, 2021/09/21
- [PULL v2 13/21] hw/riscv: virt: Add optional ACLINT support to virt machine, Alistair Francis, 2021/09/21
- [PULL v2 14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set, Alistair Francis, 2021/09/21
- [PULL v2 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions, Alistair Francis, 2021/09/21
- [PULL v2 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions, Alistair Francis, 2021/09/21
- [PULL v2 17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer, Alistair Francis, 2021/09/21
- [PULL v2 18/21] docs/system/riscv: sifive_u: Update U-Boot instructions, Alistair Francis, 2021/09/21
- [PULL v2 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped, Alistair Francis, 2021/09/21
- [PULL v2 20/21] target/riscv: csr: Rename HCOUNTEREN_CY and friends, Alistair Francis, 2021/09/21
- [PULL v2 21/21] hw/riscv: opentitan: Correct the USB Dev address, Alistair Francis, 2021/09/21
- Re: [PULL v2 00/21] riscv-to-apply queue, Richard Henderson <=

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