Re: [PATCH v5 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler for loongarch64 hosts

[Philippe Mathieu-Daudé]

On 9/24/21 19:25, WANG Xuerui wrote:
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   accel/tcg/user-exec.c | 73 +++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 73 insertions(+)
>
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 8fed542622..38d4ad8a7d 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -878,6 +878,79 @@ int cpu_signal_handler(int host_signum, void *pinfo,
>       return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
>   }
>   
> +#elif defined(__loongarch64)
> +
> +int cpu_signal_handler(int host_signum, void *pinfo,
> +                       void *puc)
> +{
> +    siginfo_t *info = pinfo;
> +    ucontext_t *uc = puc;
> +    greg_t pc = uc->uc_mcontext.__pc;
> +    uint32_t insn = *(uint32_t *)pc;
> +    int is_write = 0;

Predating this patch, but is_write should be boolean.

Note this will clash with Richard signal rework:
https://lists.gnu.org/archive/html/qemu-devel/2021-09/msg04804.html

Anyhow,
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> +
> +    /* Detect store by reading the instruction at the program counter.  */
> +    switch ((insn >> 26) & 0b111111) {
> +    case 0b001000: /* {ll,sc}.[wd] */
> +        switch ((insn >> 24) & 0b11) {
> +        case 0b01: /* sc.w */
> +        case 0b11: /* sc.d */
> +            is_write = 1;
> +            break;
> +        }
> +        break;
> +    case 0b001001: /* {ld,st}ox4.[wd] ({ld,st}ptr.[wd]) */
> +        switch ((insn >> 24) & 0b11) {
> +        case 0b01: /* stox4.w (stptr.w) */
> +        case 0b11: /* stox4.d (stptr.d) */
> +            is_write = 1;
> +            break;
> +        }
> +        break;
> +    case 0b001010: /* {ld,st}.* family */
> +        switch ((insn >> 22) & 0b1111) {
> +        case 0b0100: /* st.b */
> +        case 0b0101: /* st.h */
> +        case 0b0110: /* st.w */
> +        case 0b0111: /* st.d */
> +        case 0b1101: /* fst.s */
> +        case 0b1111: /* fst.d */
> +            is_write = 1;
> +            break;
> +        }
> +        break;
> +    case 0b001110: /* indexed, atomic, bounds-checking memory operations */
> +        uint32_t sel = (insn >> 15) & 0b11111111111;
> +
> +        switch (sel) {
> +        case 0b00000100000: /* stx.b */
> +        case 0b00000101000: /* stx.h */
> +        case 0b00000110000: /* stx.w */
> +        case 0b00000111000: /* stx.d */
> +        case 0b00001110000: /* fstx.s */
> +        case 0b00001111000: /* fstx.d */
> +        case 0b00011101100: /* fstgt.s */
> +        case 0b00011101101: /* fstgt.d */
> +        case 0b00011101110: /* fstle.s */
> +        case 0b00011101111: /* fstle.d */
> +        case 0b00011111000: /* stgt.b */
> +        case 0b00011111001: /* stgt.h */
> +        case 0b00011111010: /* stgt.w */
> +        case 0b00011111011: /* stgt.d */
> +        case 0b00011111100: /* stle.b */
> +        case 0b00011111101: /* stle.h */
> +        case 0b00011111110: /* stle.w */
> +        case 0b00011111111: /* stle.d */
> +        case 0b00011000000 ... 0b00011100011: /* am* insns */
> +            is_write = 1;
> +            break;
> +        }
> +        break;
> +    }
> +
> +    return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
> +}
> +
>   #else
>   
>   #error host CPU specific signal handler needed