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[PULL 15/19] aspeed/hace: Support HMAC Key Buffer register.
From: |
Cédric Le Goater |
Subject: |
[PULL 15/19] aspeed/hace: Support HMAC Key Buffer register. |
Date: |
Tue, 3 May 2022 08:58:44 +0200 |
From: Steven Lee <steven_lee@aspeedtech.com>
Support HACE28: Hash HMAC Key Buffer Base Address Register.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220426021120.28255-2-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/misc/aspeed_hace.h | 1 +
hw/misc/aspeed_hace.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h
index 94d5ada95fa2..2242945eb426 100644
--- a/include/hw/misc/aspeed_hace.h
+++ b/include/hw/misc/aspeed_hace.h
@@ -37,6 +37,7 @@ struct AspeedHACEClass {
uint32_t src_mask;
uint32_t dest_mask;
+ uint32_t key_mask;
uint32_t hash_mask;
};
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 10f00e65f4e1..59fe5bfca227 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -27,6 +27,7 @@
#define R_HASH_SRC (0x20 / 4)
#define R_HASH_DEST (0x24 / 4)
+#define R_HASH_KEY_BUFF (0x28 / 4)
#define R_HASH_SRC_LEN (0x2c / 4)
#define R_HASH_CMD (0x30 / 4)
@@ -210,6 +211,9 @@ static void aspeed_hace_write(void *opaque, hwaddr addr,
uint64_t data,
case R_HASH_DEST:
data &= ahc->dest_mask;
break;
+ case R_HASH_KEY_BUFF:
+ data &= ahc->key_mask;
+ break;
case R_HASH_SRC_LEN:
data &= 0x0FFFFFFF;
break;
@@ -333,6 +337,7 @@ static void aspeed_ast2400_hace_class_init(ObjectClass
*klass, void *data)
ahc->src_mask = 0x0FFFFFFF;
ahc->dest_mask = 0x0FFFFFF8;
+ ahc->key_mask = 0x0FFFFFC0;
ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */
}
@@ -351,6 +356,7 @@ static void aspeed_ast2500_hace_class_init(ObjectClass
*klass, void *data)
ahc->src_mask = 0x3fffffff;
ahc->dest_mask = 0x3ffffff8;
+ ahc->key_mask = 0x3FFFFFC0;
ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */
}
@@ -369,6 +375,7 @@ static void aspeed_ast2600_hace_class_init(ObjectClass
*klass, void *data)
ahc->src_mask = 0x7FFFFFFF;
ahc->dest_mask = 0x7FFFFFF8;
+ ahc->key_mask = 0x7FFFFFF8;
ahc->hash_mask = 0x00147FFF;
}
--
2.35.1
- [PULL 09/19] aspeed/timer: Add AST1030 support, (continued)
- [PULL 09/19] aspeed/timer: Add AST1030 support, Cédric Le Goater, 2022/05/03
- [PULL 11/19] aspeed/soc : Add AST1030 support, Cédric Le Goater, 2022/05/03
- [PULL 10/19] aspeed/scu: Add AST1030 support, Cédric Le Goater, 2022/05/03
- [PULL 12/19] aspeed: Add an AST1030 eval board, Cédric Le Goater, 2022/05/03
- [PULL 18/19] hw/gpio/aspeed_gpio: Fix QOM pin property, Cédric Le Goater, 2022/05/03
- [PULL 13/19] test/avocado/machine_aspeed.py: Add ast1030 test case, Cédric Le Goater, 2022/05/03
- [PULL 17/19] tests/qtest: Add test for Aspeed HACE accumulative mode, Cédric Le Goater, 2022/05/03
- [PULL 14/19] hw/arm/aspeed: fix AST2500/AST2600 EVB fmc model, Cédric Le Goater, 2022/05/03
- [PULL 16/19] aspeed/hace: Support AST2600 HACE, Cédric Le Goater, 2022/05/03
- [PULL 19/19] aspeed/hace: Support AST1030 HACE, Cédric Le Goater, 2022/05/03
- [PULL 15/19] aspeed/hace: Support HMAC Key Buffer register.,
Cédric Le Goater <=
- Re: [PULL 00/19] aspeed queue, Richard Henderson, 2022/05/03