[PATCH] linux-user: Expose risc-v V and H isa bit in get_elf_hwcap()

[nihui]

This patch brings the optional risc-v vector and hypervisor bits
in hwcap so that application could detect these isa support from
/proc/self/auxv correctly in qemu userspace mode.

Signed-off-by: Ni Hui <shuizhuyuanluo@126.com>
---
 linux-user/elfload.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 61063fd974..3f0ef2b8f6 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1484,7 +1484,8 @@ static uint32_t get_elf_hwcap(void)
 #define MISA_BIT(EXT) (1 << (EXT - 'A'))
     RISCVCPU *cpu = RISCV_CPU(thread_cpu);
     uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
-                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
+                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C')
+                    | MISA_BIT('V') | MISA_BIT('H');
 
     return cpu->env.misa_ext & mask;
 #undef MISA_BIT
-- 
2.25.1