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[PATCH v2 6/8] target/riscv: Add dummy mcountinhibit CSR for priv spec v
From: |
Anup Patel |
Subject: |
[PATCH v2 6/8] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher |
Date: |
Wed, 11 May 2022 20:15:26 +0530 |
The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
implementation that don't want to implement can simply have a dummy
mcountinhibit which always zero.
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in
the CSR ops.")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 2 ++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 4d04b20d06..4a55c6a709 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -159,6 +159,9 @@
#define CSR_MTVEC 0x305
#define CSR_MCOUNTEREN 0x306
+/* Machine Counter Setup */
+#define CSR_MCOUNTINHIBIT 0x320
+
/* 32-bit only */
#define CSR_MSTATUSH 0x310
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 2bf0a97196..e144ce7135 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3391,6 +3391,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie
},
[CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec
},
[CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren,
write_mcounteren },
+ [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_zero, write_ignore,
+ .min_priv_ver =
PRIV_VERSION_1_11_0 },
[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush,
write_mstatush },
--
2.34.1
- [PATCH v2 1/8] target/riscv: Fix csr number based privilege checking, (continued)
- [PATCH v2 1/8] target/riscv: Fix csr number based privilege checking, Anup Patel, 2022/05/11
- [PATCH v2 2/8] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode, Anup Patel, 2022/05/11
- [PATCH v2 3/8] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps, Anup Patel, 2022/05/11
- [PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt(), Anup Patel, 2022/05/11
- [PATCH v2 5/8] target/riscv: Don't force update priv spec version to latest, Anup Patel, 2022/05/11
- [PATCH v2 6/8] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher,
Anup Patel <=
- [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match, Anup Patel, 2022/05/11
[PATCH v2 8/8] hw/riscv: virt: Fix interrupt parent for dynamic platform devices, Anup Patel, 2022/05/11
Re: [PATCH v2 0/8] QEMU RISC-V nested virtualization fixes, Alistair Francis, 2022/05/24